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TPD6S300ARUKR

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Texas Instruments Surge Suppressors, WQFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPD6S300ARUKR

Texas Instruments · Surge Suppressors · WQFN-20-EP(3x3)

TPD6S300ARUKR from Texas Instruments, in a WQFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C_SBU1 bidirectional Connector side of the SBU1 OVP FET; connect to either SBU pin of the USB Type-C connector, or to a USB2.0 pin to protect USB2.0 instead (absolute max 24 V).
2 C_SBU2 bidirectional Connector side of the SBU2 OVP FET; connect to either SBU pin of the USB Type-C connector, or to a USB2.0 pin to protect USB2.0 instead (absolute max 24 V).
3 VBIAS passive Pin for ESD support capacitor; place a 0.1-µF capacitor on this pin to ground (absolute max 24 V).
4 C_CC1 bidirectional Connector side of the CC1 OVP FET; connect to either CC pin of the USB Type-C connector (absolute max 24 V).
5 C_CC2 bidirectional Connector side of the CC2 OVP FET; connect to either CC pin of the USB Type-C connector (absolute max 24 V).
6 RPD_G2 bidirectional Short to C_CC2 if dead battery resistors are needed; if not needed, short pin to GND (absolute max 24 V).
7 RPD_G1 bidirectional Short to C_CC1 if dead battery resistors are needed; if not needed, short pin to GND (absolute max 24 V).
8 GND power_in Ground.
9 FLT output Open drain for fault reporting (absolute max 6 V).
10 VPWR power_in 2.7-V to 4.5-V power supply.
11 CC2 bidirectional System side of the CC2 OVP FET; connect to either CC pin of the CC/PD controller.
12 CC1 bidirectional System side of the CC1 OVP FET; connect to either CC pin of the CC/PD controller.
13 GND power_in Ground.
14 SBU2 bidirectional System side of the SBU2 OVP FET; connect to either SBU pin of the SBU MUX, or to a USB2.0 Phy pin when protecting USB2.0 pins.
15 SBU1 bidirectional System side of the SBU1 OVP FET; connect to either SBU pin of the SBU MUX, or to a USB2.0 Phy pin when protecting USB2.0 pins.
16 N.C. unconnected Unused pin; connect to Ground.
17 N.C. unconnected Unused pin; connect to Ground.
18 GND power_in Ground.
19 D2 bidirectional USB2.0 IEC ESD protection; connect to any of the USB2.0 pins of the USB Type-C connector.
20 D1 bidirectional USB2.0 IEC ESD protection; connect to any of the USB2.0 pins of the USB Type-C connector.
21 Thermal Pad power_in Internally connected to GND; used as a heatsink, connect to the PCB GND plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-20-EP(3x3)
Category TVS/Fuse/Board Level Protection
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VPWR VPWR -0.3 5 V 6
Input voltage RPD_G1, RPD_G2 VI -0.3 24 V 6
Output voltage FLT VO -0.3 6 V 6
Output voltage VBIAS VO -0.3 24 V 6
I/O voltage D1, D2 VIO -0.3 6 V 6
I/O voltage CC1, CC2, SBU1, SBU2 VIO -0.3 6 V 6
I/O voltage C_CC1, C_CC2, C_SBU1, C_SBU2 VIO -0.3 24 V 6
Operating free air temperature TA -40 85 °C 6
Storage temperature Tstg -65 150 °C 6
ESD HBM V(ESD) -2000 2000 V ANSI/ESDA/JEDEC JS-001 6
ESD CDM V(ESD) -500 500 V JESD22-C101 6
IEC contact discharge C_CC1, C_CC2, D1, D2 V(ESD) -8000 8000 V IEC 61000-4-2 6
IEC air-gap discharge C_CC1, C_CC2, D1, D2 V(ESD) -15000 15000 V IEC 61000-4-2 6
IEC contact discharge C_SBU1, C_SBU2 V(ESD) -6000 6000 V IEC 61000-4-2 6
IEC air-gap discharge C_SBU1, C_SBU2 V(ESD) -15000 15000 V IEC 61000-4-2 6
Input voltage VPWR VPWR 2.7 3.3 4.5 V 6
Input voltage RPD_G1, RPD_G2 VI 0 5.5 V 6
FLT pull-up resistor power rail VO 2.7 5.5 V 6
I/O voltage D1, D2 VIO -0.3 5.5 V 6
I/O voltage CC1, CC2, C_CC1, C_CC2 VIO 0 5.5 V 6
I/O voltage SBU1, SBU2, C_SBU1, C_SBU2 VIO 0 4.3 V 6
VCONN current IVCONN 600 mA Current flowing into CC1/2 and out of C_CC1/2, VCCx, VC_CCx ≤ 250 mV 6
VCONN current IVCONN 1.25 A TJ ≤ 85°C 6
FLT pullup resistance 1.7 300 kΩ 7
VBIAS capacitance 0.1 µF min 35-VDC rated; 50-VDC recommended 7
VPWR capacitance 0.3 1 µF 7
Junction-to-ambient thermal resistance RθJA 45.2 °C/W RUK (WQFN) 20 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 48.8 °C/W 7
Junction-to-board thermal resistance RθJB 17.1 °C/W 7
Junction-to-top characterization parameter ψJT 0.6 °C/W 7
Junction-to-board characterization parameter ψJB 17.1 °C/W 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.7 °C/W 7
CC OVP FET on resistance, TJ ≤ 85°C RON 278 392 mΩ CCx = 5.5 V 7
CC OVP FET on resistance, TJ ≤ 105°C RON 278 415 mΩ CCx = 5.5 V 7
CC on resistance flatness RON(FLAT) 5 mΩ Sweep CCx voltage between 0 V and 1.2 V 7
CC equivalent on capacitance CON_CC 60 74 120 pF VC_CCx/VCCx = 0 V to 1.2 V, f = 400 kHz 7
Dead battery pull-down resistance RD 4.1 5.1 6.1 kΩ V_C_CCx = 2.6 V 7
Dead battery pulldown FET threshold voltage VTH_DB 0.5 0.9 1.2 V I_CC = 80 µA 7
OVP threshold on CC pins VOVPCC 5.75 6 6.2 V Place 5.5 V on C_CCx. Step up C_CCx until the FLT pin is asserted 7
Hysteresis on CC OVP VOVPCC_HYS 50 mV Place 6.5 V on C_CCx, step down until FLT deasserted 7
CC on bandwidth single ended (-3 dB) BWON 100 MHz C_CCx to CCx, 50-Ω system, Vcm = 0.1 V to 1.2 V 7
Short-to-VBUS tolerance CC pins VSTBUS_CC 24 V Hot-Plug C_CCx with a 1 meter USB Type C Cable, 30-Ω load on CCx 8
Short-to-VBUS system-side clamping voltage CC VSTBUS_CC_CLAMP 8 V Hot-Plug voltage C_CCx = 24 V. VPWR = 3.3 V. 30-Ω load on CCx 8
SBU OVP FET on resistance RON 4 6.5 Ω SBUx = 3.6 V. -40°C ≤ TJ ≤ +85°C 8
SBU on resistance flatness RON(FLAT) 0.7 1.5 Ω Sweep SBUx 0 V to 3.6 V. -40°C ≤ TJ ≤ +85°C 8
SBU equivalent on capacitance CON_SBU 6 pF VC_SBUx/VSBUx = 0.3 V to 3.6 V 8
OVP threshold on SBU pins VOVPSBU 4.35 4.5 4.7 V Place 3.6 V on C_SBUx. Step up C_SBUx until the FLT pin is asserted 8
Hysteresis on SBU OVP VOVPSBU_HYS 50 mV Place 5 V on C_CCx. Step down until FLT deasserted 8
SBU on bandwidth single ended (-3 dB) BWON 1000 MHz C_SBUx to SBUx, 50-Ω system, Vcm = 0.1 V to 3.6 V 8
Crosstalk XTALK -80 dB f = 1 MHz, Vcm1 = 3.6 V, Vcm2 = 0.3 V, open sides terminated to 50 Ω 8
Short-to-VBUS tolerance SBU pins VSTBUS_SBU 24 V Hot-Plug C_SBUx with 1 meter USB Type C Cable, 100-nF in series with 40-Ω to GND on SBUx 8
Short-to-VBUS system-side clamping voltage SBU VSTBUS_SBU_CLAMP 8 V Hot-Plug C_SBUx = 24 V. VPWR = 3.3 V. 150-nF in series with 40-Ω to GND on SBUx 8
VPWR under voltage lockout VPWR_UVLO 2.1 2.3 2.5 V Place 1 V on VPWR and raise until SBU or CC FETs turn on 8
VPWR UVLO hysteresis VPWR_UVLO_HYS 100 150 200 mV Place 3 V on VPWR and lower until FETs turn off 8
VPWR supply current IVPWR 90 135 µA VPWR = 3.3 V (typical), 4.5 V (maximum). -40°C ≤ TJ ≤ +85°C 8
CC pin leakage when powered ICC_LEAK 5 µA VPWR = 3.3 V, VC_CCx = 3.6 V, CCx floating, leakage into C_CCx 8
SBU pin leakage when powered ISBU_LEAK 3 µA VPWR = 3.3 V, VC_SBUx = 3.6 V, SBUx floating. -40°C ≤ TJ ≤ +85°C 9
CC pin leakage in OVP (into C_CCx) IC_CC_LEAK_OVP 1200 µA VPWR = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V 9
SBU pin leakage in OVP (into C_SBUx) IC_SBU_LEAK_OVP 400 µA VPWR = 0 V or 3.3 V, VC_SBUx = 24 V, SBUx = 0 V 9
CC pin leakage in OVP (out of CCx) ICC_LEAK_OVP 30 µA VPWR = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V 9
SBU pin leakage in OVP (out of SBUx) ISBU_LEAK_OVP -1 1 µA VPWR = 0 V or 3.3 V, VC_SBUx = 24 V, SBUx = 0 V 9
Dx pin leakage IDx_LEAK 1 µA V_Dx = 3.6 V 9
FLT low-level output voltage VOL 0.4 V IOL = 3 mA 9
Thermal shutdown rising threshold TSD_RISING 150 175 °C 9
Thermal shutdown falling threshold TSD_FALLING 130 140 °C 9
Thermal shutdown hysteresis TSD_HYST 35 °C 9
Dx reverse stand-off voltage Dx to GND VRWM_POS 5.5 V Dx to GND. IDX ≤ 1 µA 9
Dx break-down voltage Dx to GND VBR_POS 7 V Dx to GND. IBR = 1 mA 9
Dx to GND capacitance CIO 1.7 pF f = 1 MHz, VIO = 2.5 V 9
Dx dynamic on-resistance RDYN 0.4 Ω Dx to GND or GND to Dx 9

CAD (KiCad official)

  • Symbol: TPD6S300ARUKR
  • Footprint: Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
  • 3D model: WQFN-20-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tpd6s300arukr-etched.step / tpd6s300arukr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpd6s300arukr.step / tpd6s300arukr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 52c644af1445f90a, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF