component
TPD2EUSB30DRTR-TP-ES
Public Made by Adomby adom
ElecSuper ESD And Surge Protection (TVS/ESD), SOT-723. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPD2EUSB30DRTR-TP-ES
ElecSuper · ESD And Surge Protection (TVS/ESD) · SOT-723
TPD2EUSB30DRTR-TP-ES from ElecSuper, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IO | bidirectional | Connect to IO; this is one of the two unidirectional data lines protected by the TVS array, which has a 5 V working voltage. |
| 2 | IO | bidirectional | Connect to IO; this is the second unidirectional data line protected by the TVS array, which has a 5 V working voltage. |
| 3 | GND | power_in | Connect to GND as the ground reference for the protection array. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ElecSuper |
| Package | SOT-723 |
| Category | Circuit Protection |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Peak pulse power (tp=8/20us) | Ppk | 30 | W | tp=8/20us @25℃ | 2 | ||
| Peak pulse current (tp=8/20us) | IPP | 3 | A | tp=8/20us @25℃ | 2 | ||
| ESD (IEC61000-4-2 air discharge) | VESD | 15 | kV | @25℃; printed as ±15 kV | 2 | ||
| ESD (IEC61000-4-2 contact discharge) | VESD | 15 | kV | @25℃; printed as ±15 kV | 2 | ||
| Junction temperature | TJ | 150 | ℃ | 2 | |||
| Operating temperature | TOP | -40 | 125 | ℃ | Over operating free-air temperature range | 2 | |
| Storage temperature | TSTG | -55 | 150 | ℃ | 2 | ||
| Lead temperature | TL | 260 | ℃ | 2 | |||
| Reverse Stand-off Voltage | VRWM | 5 | V | 3 | |||
| Reverse Breakdown Voltage | VBR | 6 | V | IT=1mA | 3 | ||
| Reverse Leakage Current | IR | 1 | uA | VRWM=5V | 3 | ||
| Clamping Voltage | VC | 8.5 | 10 | V | IPP=1A; tp=8/20us | 3 | |
| Clamping Voltage | VC | 10 | 12 | V | IPP=3A; tp=8/20us | 3 | |
| Junction Capacitance IO-GND | CJ | 0.5 | 0.8 | pF | VR=0V; f=1MHz | 3 | |
| Junction Capacitance IO-IO | CJ | 0.25 | 0.4 | pF | VR=0V; f=1MHz | 3 |
CAD (KiCad official)
- Symbol:
TPD2EUSB30DRTR-TP-ES - Footprint:
Package_TO_SOT_SMD:SOT-723 - 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ElecSuper datasheet (7 pp, sha256
a0131871557a314c, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).