component

TPD2EUSB30ADRTR-N

Public Made by Adom

by adom

BORN ESD And Surge Protection (TVS/ESD), SOT-723. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPD2EUSB30ADRTR-N

BORN · ESD And Surge Protection (TVS/ESD) · SOT-723

TPD2EUSB30ADRTR-N from BORN, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O bidirectional Protected I/O line with working peak reverse voltage VRWM of 5 V and junction capacitance to GND of 0.45 pF typical (0.6 pF max) per the datasheet electrical table.
2 I/O bidirectional Protected I/O line with working peak reverse voltage VRWM of 5 V; junction capacitance between I/O pins is 0.25 pF typical (0.35 pF max) per the datasheet electrical table.
3 GND power_in Ground reference pin to which the I/O junction capacitance is specified; the datasheet gives no further limits for this pin.

Key specifications

Parameter Value
Manufacturer BORN
Package SOT-723
Category Circuit Protection
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Breakdown Voltage VBR 6 V IT = 1mA 2
Junction Capacitance between I/O pin and GND CJ 0.45 0.6 pF VDC = 0V, f = 1MHz 2
Junction Capacitance between I/O pins CO 0.25 0.35 pF VDC = 0V, f = 1MHz 2
Reverse Leakage Current IR 0.001 0.1 uA VRWM = 5V 2
Clamping Voltage VC 12 14 V IPP = 4A, 8/20µs 2
Operating Temperature Range TJ -55 125 ℃ 2
Storage Temperature Range TSTG -55 150 ℃ 2
ESD per IEC 61000-4-2 (Contact) VESD-Contact 20 KV IEC 61000-4-2 contact discharge 2
ESD per IEC 61000-4-2 (Air) VESD-Air 25 KV IEC 61000-4-2 air discharge 2
Lead Soldering Temperature TL 260 ℃ 10s 2
Reverse Working Voltage VRWM 5 V 2
Peak Pulse Power (8/20µs) PPP 56 W 8/20µs 2
Peak Pulse Current (8/20µs) IPP 4 A 8/20µs 2

CAD (KiCad official)

  • Symbol: TPD2EUSB30ADRTR-N
  • Footprint: Package_TO_SOT_SMD:SOT-723
  • 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tpd2eusb30adrtr-n-etched.step / tpd2eusb30adrtr-n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpd2eusb30adrtr-n.step / tpd2eusb30adrtr-n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BORN datasheet (4 pp, sha256 c02cafe8f621ea9f, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF