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TPD2E009DRTR
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Leiditech ESD And Surge Protection (TVS/ESD), SOT-723. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPD2E009DRTR
Leiditech · ESD And Surge Protection (TVS/ESD) · SOT-723
TPD2E009DRTR from Leiditech, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IO1 | passive | ESD-protected line 1 (steering-diode node), rated for 5V reverse working voltage, 100 W peak pulse power (8/20µs) and ±17kV air / ±10kV contact ESD per IEC 61000-4-2. |
| 2 | IO2 | passive | ESD-protected line 2 (steering-diode node), rated for 5V reverse working voltage, 100 W peak pulse power (8/20µs) and ±17kV air / ±10kV contact ESD per IEC 61000-4-2. |
| 3 | GND | power_in | Common cathode node of the internal TVS diode, shown on the pin configuration as the shared reference pin for both protected lines, with 0.3 pF typical junction capacitance per line at 0V, 1MHz. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | SOT-723 |
| Category | Circuit Protection |
| Pins | 3 |
CAD (KiCad official)
- Symbol:
TPD2E009DRTR - Footprint:
Package_TO_SOT_SMD:SOT-723 - 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tpd2e009drtr-etched.step/tpd2e009drtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpd2e009drtr.step/tpd2e009drtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leiditech datasheet (6 pp, sha256
8c1552d102b004d3, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPD2E009DRTR
**Leiditech** · ESD And Surge Protection (TVS/ESD) · SOT-723
TPD2E009DRTR from Leiditech, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IO1 | passive | ESD-protected line 1 (steering-diode node), rated for 5V reverse working voltage, 100 W peak pulse power (8/20µs) and ±17kV air / ±10kV contact ESD per IEC 61000-4-2. |
| 2 | IO2 | passive | ESD-protected line 2 (steering-diode node), rated for 5V reverse working voltage, 100 W peak pulse power (8/20µs) and ±17kV air / ±10kV contact ESD per IEC 61000-4-2. |
| 3 | GND | power_in | Common cathode node of the internal TVS diode, shown on the pin configuration as the shared reference pin for both protected lines, with 0.3 pF typical junction capacitance per line at 0V, 1MHz. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | SOT-723 |
| Category | Circuit Protection |
| Pins | 3 |
## CAD (KiCad official)
- Symbol: `TPD2E009DRTR`
- Footprint: `Package_TO_SOT_SMD:SOT-723`
- 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tpd2e009drtr-etched.step` / `tpd2e009drtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpd2e009drtr.step` / `tpd2e009drtr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Leiditech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603047863774048256) (6 pp, sha256 `8c1552d102b004d3`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpd2e009drtr-datasheet.pdf)