component
TPCA8053-H-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, DFN5x6-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPCA8053-H-VB
VBsemi Elec · MOSFETs · DFN5x6-8
TPCA8053-H-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET (pin 1 marked with dot); continuous source current 50 A (package limited). |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to the same source as pins 1 and 3. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to the same source as pins 1 and 2. |
| 4 | G | input | Gate terminal; gate-source voltage limited to ±20 V. |
| 5 | D | passive | Drain terminal; VDS rated 60 V, pulsed drain current 100 A. |
| 6 | D | passive | Drain terminal, tied to the same drain as pins 5, 7 and 8. |
| 7 | D | passive | Drain terminal, tied to the same drain as pins 5, 6 and 8. |
| 8 | D | passive | Drain terminal, tied to the same drain as pins 5, 6 and 7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | DFN5x6-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | VDS | 60 | V | VGS = 0 V, ID = 250 µA | 2 | ||
| Gate Threshold Voltage | VGS(th) | 1 | 2 | 3 | V | VDS = VGS, ID = 250 µA | 2 |
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 60 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current (125 °C) | IDSS | 50 | µA | VDS = 60 V, VGS = 0 V, TJ = 125 °C | 2 | ||
| Zero Gate Voltage Drain Current (175 °C) | IDSS | 250 | µA | VDS = 60 V, VGS = 0 V, TJ = 175 °C | 2 | ||
| On-State Drain Current | ID(on) | 60 | A | VDS = 5 V, VGS = 10 V | 2 | ||
| Drain-Source On-State Resistance (125 °C) | RDS(on) | 0.016 | Ω | VGS = 10 V, ID = 20 A, TJ = 125 °C | 2 | ||
| Drain-Source On-State Resistance (175 °C) | RDS(on) | 0.02 | Ω | VGS = 10 V, ID = 20 A, TJ = 175 °C | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.013 | Ω | VGS = 4.5 V, ID = 15 A | 2 | ||
| Forward Transconductance | gfs | 60 | S | VDS = 15 V, ID = 20 A | 2 | ||
| Total Gate Charge | Qg | 47 | 70 | nC | VDS = 30 V, VGS = 10 V, ID = 50 A | 2 | |
| Turn-On Delay Time | td(on) | 10 | 20 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 | |
| Rise Time | tr | 15 | 25 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 35 | 50 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 | |
| Fall Time | tf | 20 | 30 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 | |
| Reverse Recovery Time | trr | 45 | 100 | ns | IF = 20 A, di/dt = 100 A/µs | 2 | |
| Pulsed Source Current | ISM | 60 | A | TC = 25 °C | 2 | ||
| Gate-Source Voltage | VGS | -20 | 20 | V | TC = 25 °C | 1 | |
| Pulsed Drain Current | IDM | 100 | A | TC = 25 °C | 1 | ||
| Continuous Source Current (Diode Conduction) | IS | 50 | A | TC = 25 °C, package limited | 1 | ||
| Avalanche Current | IAS | 50 | A | TC = 25 °C | 1 | ||
| Single Avalanche Energy | EAS | 125 | mJ | L = 0.1 mH, duty cycle ≤ 1 % | 1 | ||
| Maximum Power Dissipation | PD | 136 | W | TC = 25 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 175 | °C | 1 | ||
| Maximum Junction-to-Ambient (t ≤ 10 s) | RthJA | 15 | 18 | °C/W | t ≤ 10 sec, surface mounted on 1" x 1" FR4 board | 1 | |
| Maximum Junction-to-Ambient (steady state) | RthJA | 40 | 50 | °C/W | Steady State, surface mounted on 1" x 1" FR4 board | 1 | |
| Maximum Junction-to-Case | RthJC | 0.85 | 1.1 | °C/W | 1 | ||
| Input Capacitance | Ciss | 2650 | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 | ||
| Output Capacitance | Coss | 470 | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 | ||
| Reverse Transfer Capacitance | Crss | 225 | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 | ||
| Gate-Source Charge | Qgs | 10 | nC | VDS = 30 V, VGS = 10 V, ID = 50 A | 2 | ||
| Gate-Drain Charge | Qgd | 12 | nC | VDS = 30 V, VGS = 10 V, ID = 50 A | 2 |
CAD (KiCad official)
- Symbol:
TPCA8053-H-VB - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN5x6-8 (KiCad packages3D, STEP)
- 3D model files:
tpca8053-h-vb-etched.step/tpca8053-h-vb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpca8053-h-vb.step/tpca8053-h-vb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VBsemi Elec datasheet (7 pp, sha256
29d01a2b026274b1, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPCA8053-H-VB
**VBsemi Elec** · MOSFETs · DFN5x6-8
TPCA8053-H-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET (pin 1 marked with dot); continuous source current 50 A (package limited). |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to the same source as pins 1 and 3. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to the same source as pins 1 and 2. |
| 4 | G | input | Gate terminal; gate-source voltage limited to ±20 V. |
| 5 | D | passive | Drain terminal; VDS rated 60 V, pulsed drain current 100 A. |
| 6 | D | passive | Drain terminal, tied to the same drain as pins 5, 7 and 8. |
| 7 | D | passive | Drain terminal, tied to the same drain as pins 5, 6 and 8. |
| 8 | D | passive | Drain terminal, tied to the same drain as pins 5, 6 and 7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | DFN5x6-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | VDS | 60 | | | V | VGS = 0 V, ID = 250 µA | 2 |
| Gate Threshold Voltage | VGS(th) | 1 | 2 | 3 | V | VDS = VGS, ID = 250 µA | 2 |
| Gate-Body Leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | µA | VDS = 60 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current (125 °C) | IDSS | | | 50 | µA | VDS = 60 V, VGS = 0 V, TJ = 125 °C | 2 |
| Zero Gate Voltage Drain Current (175 °C) | IDSS | | | 250 | µA | VDS = 60 V, VGS = 0 V, TJ = 175 °C | 2 |
| On-State Drain Current | ID(on) | 60 | | | A | VDS = 5 V, VGS = 10 V | 2 |
| Drain-Source On-State Resistance (125 °C) | RDS(on) | | | 0.016 | Ω | VGS = 10 V, ID = 20 A, TJ = 125 °C | 2 |
| Drain-Source On-State Resistance (175 °C) | RDS(on) | | | 0.02 | Ω | VGS = 10 V, ID = 20 A, TJ = 175 °C | 2 |
| Drain-Source On-State Resistance | RDS(on) | | | 0.013 | Ω | VGS = 4.5 V, ID = 15 A | 2 |
| Forward Transconductance | gfs | | 60 | | S | VDS = 15 V, ID = 20 A | 2 |
| Total Gate Charge | Qg | | 47 | 70 | nC | VDS = 30 V, VGS = 10 V, ID = 50 A | 2 |
| Turn-On Delay Time | td(on) | | 10 | 20 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 |
| Rise Time | tr | | 15 | 25 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 |
| Turn-Off Delay Time | td(off) | | 35 | 50 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 |
| Fall Time | tf | | 20 | 30 | ns | VDD = 30 V, RL = 0.6 Ω, ID ≅ 50 A, VGEN = 10 V, Rg = 2.5 Ω | 2 |
| Reverse Recovery Time | trr | | 45 | 100 | ns | IF = 20 A, di/dt = 100 A/µs | 2 |
| Pulsed Source Current | ISM | | | 60 | A | TC = 25 °C | 2 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | TC = 25 °C | 1 |
| Pulsed Drain Current | IDM | | | 100 | A | TC = 25 °C | 1 |
| Continuous Source Current (Diode Conduction) | IS | | | 50 | A | TC = 25 °C, package limited | 1 |
| Avalanche Current | IAS | | | 50 | A | TC = 25 °C | 1 |
| Single Avalanche Energy | EAS | | | 125 | mJ | L = 0.1 mH, duty cycle ≤ 1 % | 1 |
| Maximum Power Dissipation | PD | | | 136 | W | TC = 25 °C | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 175 | °C | | 1 |
| Maximum Junction-to-Ambient (t ≤ 10 s) | RthJA | | 15 | 18 | °C/W | t ≤ 10 sec, surface mounted on 1" x 1" FR4 board | 1 |
| Maximum Junction-to-Ambient (steady state) | RthJA | | 40 | 50 | °C/W | Steady State, surface mounted on 1" x 1" FR4 board | 1 |
| Maximum Junction-to-Case | RthJC | | 0.85 | 1.1 | °C/W | | 1 |
| Input Capacitance | Ciss | | 2650 | | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 |
| Output Capacitance | Coss | | 470 | | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 |
| Reverse Transfer Capacitance | Crss | | 225 | | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 |
| Gate-Source Charge | Qgs | | 10 | | nC | VDS = 30 V, VGS = 10 V, ID = 50 A | 2 |
| Gate-Drain Charge | Qgd | | 12 | | nC | VDS = 30 V, VGS = 10 V, ID = 50 A | 2 |
## CAD (KiCad official)
- Symbol: `TPCA8053-H-VB`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN5x6-8 (KiCad packages3D, STEP)
- 3D model files: `tpca8053-h-vb-etched.step` / `tpca8053-h-vb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpca8053-h-vb.step` / `tpca8053-h-vb.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VBsemi Elec datasheet](docs/tpca8053-h-vb-datasheet.pdf) (7 pp, sha256 `29d01a2b026274b1`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpca8053-h-vb-datasheet.pdf)