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TPA3112D1PWPR

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Texas Instruments Audio Amplifiers, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPA3112D1PWPR

Texas Instruments · Audio Amplifiers · HTSSOP-28

TPA3112D1PWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD input Shutdown logic input; LOW = outputs Hi-Z (shutdown), HIGH = outputs enabled; TTL logic levels with compliance to AVCC; never leave unconnected.
2 FAULT output Open-drain output indicating short-circuit or DC-detect fault (active LOW); voltage compliant to AVCC; connect to SD for auto-recovery from short-circuit faults, otherwise cycle PVCC to clear.
3 GND power_in Local analog ground; connect to system ground plane.
4 GND power_in Local analog ground; connect to system ground plane.
5 GAIN0 input Gain select LSB; TTL logic levels with compliance to AVCC; sets amplifier gain (20/26/32/36 dB) per gain table; slew rate must not exceed 10 V/ms.
6 GAIN1 input Gain select MSB; TTL logic levels with compliance to AVCC; sets amplifier gain (20/26/32/36 dB) per gain table; slew rate must not exceed 10 V/ms.
7 AVCC power_in Analog supply; 8 V to 26 V operating range; decouple with 10-µF capacitor placed close to pin.
8 AGND power_in Analog supply ground; connect to the exposed thermal pad.
9 GVDD power_out Internal LDO output supplying high-side FET gate drive; nominal 7 V (6.5 V min, 7.3 V max at IGVDD = 2 mA); add 1-µF capacitor to ground; may also supply PLIMIT resistor divider.
10 PLIMIT input Power limit adjust input; virtual output rail = 4 × VPLIMIT; connect directly to GVDD for no limiting; add 1-µF capacitor to ground; rated −0.3 V to GVDD + 0.3 V.
11 INN input Negative differential audio input; internally biased at 3 V; input impedance 9 kΩ to 60 kΩ depending on gain setting; rated −0.3 V to 6.3 V.
12 INP input Positive differential audio input; internally biased at 3 V; input impedance 9 kΩ to 60 kΩ depending on gain setting; rated −0.3 V to 6.3 V.
13 NC unconnected No internal connection; leave unconnected.
14 AVCC power_in Analog supply; 8 V to 26 V operating range; voltage slew rate must not exceed 10 V/ms without a 100-kΩ series resistor.
15 PVCC power_in H-bridge power supply; 8 V to 26 V operating range; all PVCC pins connected internally; decouple with 220-µF bulk and 0.1-µF ceramic capacitors placed as close as possible to pin.
16 PVCC power_in H-bridge power supply; 8 V to 26 V operating range; all PVCC pins connected internally; decouple with 220-µF bulk and 0.1-µF ceramic capacitors placed as close as possible to pin.
17 BSP passive Bootstrap I/O for positive high-side FET; connect a 470-nF ceramic capacitor rated ≥16 V from OUTP to BSP to form the floating gate-drive supply.
18 OUTP output Class-D H-bridge positive output; switches 0 V to PVCC at ~310 kHz; protected against shorts to GND, VCC, and output-to-output with auto-recovery option.
19 PGND power_in Power ground for the H-bridges; connect to solid power ground plane.
20 OUTP output Class-D H-bridge positive output; switches 0 V to PVCC at ~310 kHz; protected against shorts to GND, VCC, and output-to-output with auto-recovery option.
21 BSP passive Bootstrap I/O for positive high-side FET; connect a 470-nF ceramic capacitor rated ≥16 V from OUTP to BSP to form the floating gate-drive supply.
22 BSN passive Bootstrap I/O for negative high-side FET; connect a 470-nF ceramic capacitor rated ≥16 V from OUTN to BSN to form the floating gate-drive supply.
23 OUTN output Class-D H-bridge negative output; switches 0 V to PVCC at ~310 kHz; protected against shorts to GND, VCC, and output-to-output with auto-recovery option.
24 PGND power_in Power ground for the H-bridges; connect to solid power ground plane.
25 OUTN output Class-D H-bridge negative output; switches 0 V to PVCC at ~310 kHz; protected against shorts to GND, VCC, and output-to-output with auto-recovery option.
26 BSN passive Bootstrap I/O for negative high-side FET; connect a 470-nF ceramic capacitor rated ≥16 V from OUTN to BSN to form the floating gate-drive supply.
27 PVCC power_in H-bridge power supply; 8 V to 26 V operating range; all PVCC pins connected internally; decouple with 220-µF bulk and 0.1-µF ceramic capacitors placed as close as possible to pin.
28 PVCC power_in H-bridge power supply; 8 V to 26 V operating range; all PVCC pins connected internally; decouple with 220-µF bulk and 0.1-µF ceramic capacitors placed as close as possible to pin.
29 PowerPAD power_in Exposed thermal pad (GND); must be soldered to PCB thermal land (6.46 mm × 2.35 mm) with seven rows of solid vias for thermal and electrical ground connection; connect to AGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28
Category Amplifiers/Comparators
Pins 29

CAD (KiCad official)

  • Symbol: TPA3112D1PWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)
  • 3D model files: tpa3112d1pwpr-etched.step / tpa3112d1pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpa3112d1pwpr.step / tpa3112d1pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 ec7f17b2fb89aa52, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF