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TPA3111D1PWP
Public Made by Adomby adom
Texas Instruments Audio Power OpAmps, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPA3111D1PWP
Texas Instruments · Audio Power OpAmps · HTSSOP-28-EP
TPA3111D1PWP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SD | input | Shutdown logic input for the audio amplifier (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL logic levels with compliance to AVCC. |
| 2 | FAULT | output | Open-drain output showing short-circuit or DC Detect fault status, voltage compliant to AVCC; connect to SD for short-circuit auto-recovery, otherwise cycle PVCC to reset faults. |
| 3 | GND | power_in | Connect to local ground. |
| 4 | GND | power_in | Connect to local ground. |
| 5 | GAIN0 | input | Gain select least significant bit, TTL logic levels with compliance to AVCC. |
| 6 | GAIN1 | input | Gain select most significant bit, TTL logic levels with compliance to AVCC. |
| 7 | AVCC | power_in | Analog supply; a 100-kΩ resistor in series with AVCC is needed if the PVCC slew rate is greater than 10 V/ms. |
| 8 | AGND | power_in | Analog supply ground, connect to the thermal pad. |
| 9 | GVDD | power_out | High-side FET gate drive supply, nominal 7 V, can also supply the PLIMIT divider; add a 1-µF capacitor to ground. |
| 10 | PLIMIT | input | Power limit level adjust; connect directly to GVDD for no power limiting and add a 1-µF capacitor to ground. |
| 11 | INN | input | Negative audio input, biased at 3 V. |
| 12 | INP | input | Positive audio input, biased at 3 V. |
| 13 | NC | unconnected | Not connected. |
| 14 | AVCC | power_in | Connect AVCC supply to this pin; a 100-kΩ resistor in series is needed if the PVCC slew rate exceeds 10 V/ms. |
| 15 | PVCC | power_in | Power supply for H-bridge, PVCC pins are connected internally. |
| 16 | PVCC | power_in | Power supply for H-bridge, PVCC pins are connected internally. |
| 17 | BSP | passive | Bootstrap I/O for positive high-side FET. |
| 18 | OUTP | output | Class-D H-bridge positive output. |
| 19 | PGND | power_in | Power ground for the H-bridges. |
| 20 | OUTP | output | Class-D H-bridge positive output. |
| 21 | BSP | passive | Bootstrap I/O for positive high-side FET. |
| 22 | BSN | passive | Bootstrap I/O for negative high-side FET. |
| 23 | OUTN | output | Class-D H-bridge negative output. |
| 24 | PGND | power_in | Power ground for the H-bridges. |
| 25 | OUTN | output | Class-D H-bridge negative output. |
| 26 | BSN | passive | Bootstrap I/O for negative high-side FET. |
| 27 | PVCC | power_in | Power supply for H-bridge, PVCC pins are connected internally. |
| 28 | PVCC | power_in | Power supply for H-bridge, PVCC pins are connected internally. |
| 29 | GND | power_in | Exposed PowerPAD thermal pad that must be connected to a thermally dissipating ground plane for proper power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Operational Amplifier/Comparator |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage PVCC, AVCC | VCC | 8 | 26 | V | Over operating free-air temperature range | 5 | |
| High-level input voltage SD, GAIN0, GAIN1 | VIH | 2 | V | 5 | |||
| Low-level input voltage SD, GAIN0, GAIN1 | VIL | 0.8 | V | 5 | |||
| Low-level output voltage FAULT | VOL | 0.8 | V | RPULLUP = 100 kΩ, VCC = 26 V | 5 | ||
| High-level input current SD, GAIN0, GAIN1 | IIH | 50 | µA | VI = 2 V, VCC = 18 V | 5 | ||
| Low-level input current SD, GAIN0, GAIN1 | IIL | 5 | µA | VI = 0.8 V, VCC = 18 V | 5 | ||
| Supply voltage AVCC, PVCC (absolute maximum) | VCC | -0.3 | 30 | V | 4 | ||
| Interface pin voltage SD, FAULT, GAIN0, GAIN1, AVCC (pin 14); max printed as VCC + 0.3 | VI | -0.3 | V | Voltage slew rate <10 V/ms | 4 | ||
| Interface pin voltage PLIMIT; max printed as VGVDD + 0.3 | VI | -0.3 | V | 4 | |||
| Interface pin voltage INN, INP | VI | -0.3 | 6.3 | V | 4 | ||
| Minimum load resistance, BTL | RL | 3.2 | Ω | 4 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Electrostatic discharge, human-body model (HBM) | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), JEDEC Standard 22 Test Method A114-B | 4 | |
| Electrostatic discharge, charged-device model (CDM) | V(ESD) | -500 | 500 | V | Charged-device model (CDM) | 4 | |
| Class-D output offset voltage (measured differentially) | /VOS/ | 1.5 | 15 | mA | VCC = 24 V; TA = 25°C, RL = 8 Ω; VI = 0 V, Gain = 36 dB | 5 | |
| Gain, VGAIN1 = 0.8 V, VGAIN0 = 0.8 V | G | 19 | 20 | 21 | dB | VCC = 24 V; TA = 25°C, RL = 8 Ω; VGAIN1 = 0.8 V, VGAIN0 = 0.8 V | 5 |
| Gain, VGAIN1 = 0.8 V, VGAIN0 = 2 V | G | 25 | 26 | 27 | dB | VCC = 24 V; TA = 25°C, RL = 8 Ω; VGAIN0 = 2 V (VGAIN1 = 0.8 V) | 5 |
| Gain, VGAIN1 = 2 V, VGAIN0 = 0.8 V | G | 31 | 32 | 33 | dB | VCC = 24 V; TA = 25°C, RL = 8 Ω; VGAIN0 = 0.8 V (VGAIN1 = 2 V) | 5 |
| Gain, VGAIN1 = 2 V, VGAIN0 = 2 V | G | 35 | 36 | 37 | dB | VCC = 24 V; TA = 25°C, RL = 8 Ω; VGAIN0 = 2 V (VGAIN1 = 2 V) | 5 |
| Gate drive supply | VGVDD | 6.5 | 6.9 | 7.3 | V | VCC = 24 V; TA = 25°C, RL = 8 Ω; IGVDD = 2 mA | 5 |
| Gain, VGAIN1 = 0.8 V, VGAIN0 = 0.8 V | G | 19 | 20 | 21 | dB | VCC = 12 V; TA = 25°C, RL = 8 Ω; VGAIN1 = 0.8 V, VGAIN0 = 0.8 V | 6 |
| Gain, VGAIN1 = 0.8 V, VGAIN0 = 2 V | G | 25 | 26 | 27 | dB | VCC = 12 V; TA = 25°C, RL = 8 Ω; VGAIN0 = 2 V (VGAIN1 = 0.8 V) | 6 |
| Gain, VGAIN1 = 2 V, VGAIN0 = 0.8 V | G | 31 | 32 | 33 | dB | VCC = 12 V; TA = 25°C, RL = 8 Ω; VGAIN0 = 0.8 V (VGAIN1 = 2 V) | 6 |
| Gain, VGAIN1 = 2 V, VGAIN0 = 2 V | G | 35 | 36 | 37 | dB | VCC = 12 V; TA = 25°C, RL = 8 Ω; VGAIN0 = 2 V (VGAIN1 = 2 V) | 6 |
| Gate drive supply | VGVDD | 6.5 | 6.9 | 7.3 | V | VCC = 12 V; TA = 25°C, RL = 8 Ω; IGVDD = 2 mA | 6 |
| Output voltage maximum under PLIMIT control | PLIMIT | 6.75 | 7.9 | 8.75 | V | VCC = 12 V; TA = 25°C, RL = 8 Ω; VPLIMIT = 2 V, VI = 6 V differential | 6 |
| Power supply ripple rejection | KSVR | -70 | dB | VCC = 24 V; 200-mVPP ripple from 20 Hz to 1 kHz, Gain = 20 dB, Inputs AC-coupled to AGND | 6 | ||
| Total harmonic distortion + noise | THD+N | 0.05 | % | VCC = 24 V; f = 1 kHz, PO = 5 W (half-power) | 6 | ||
| Output integrated noise | VN | 65 | µV | VCC = 24 V; 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB | 6 | ||
| Output integrated noise | VN | -80 | dBV | VCC = 24 V; 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB | 6 | ||
| Crosstalk | -70 | dB | VCC = 24 V; f = 1 kHz, VO = 1 Vrms, Gain = 20 dB | 6 | |||
| Signal-to-noise ratio | SNR | 102 | dB | VCC = 24 V; Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted | 6 | ||
| Oscillator frequency | fOSC | 250 | 310 | 350 | kHz | VCC = 24 V | 6 |
| Total harmonic distortion + noise | THD+N | 0.06 | % | VCC = 12 V; f = 1 kHz, RL = 8 Ω, PO = 5 W (half-power) | 6 | ||
| Quiescent supply current | ICC | 40 | mA | VCC = 24 V; SD = 2 V, no load, PVCC = 21 V | 5 | ||
| Quiescent supply current in shutdown mode | ICC(SD) | 400 | µA | VCC = 24 V; SD = 0.8 V, no load, PVCC = 21 V | 5 | ||
| Drain-source ON-state resistance, high side | RDS(ON) | 240 | mΩ | VCC = 24 V; IO = 500 mA, TJ = 25°C | 5 | ||
| Drain-source ON-state resistance, low side | RDS(ON) | 240 | mΩ | VCC = 24 V; IO = 500 mA, TJ = 25°C | 5 | ||
| Turn-on time | tON | 10 | ms | VCC = 24 V; VSD = 2 V | 5 | ||
| Turn-off time | tOFF | 2 | µs | VCC = 24 V; VSD = 0.8 V | 5 | ||
| Quiescent supply current | ICC | 20 | mA | VCC = 12 V; SD = 2 V, no load, PVCC = 12 V | 5 | ||
| Quiescent supply current in shutdown mode | ICC(SD) | 200 | µA | VCC = 12 V; SD = 0.8 V, no load, PVCC = 12 V | 5 | ||
| Turn-on time | tON | 10 | ms | VCC = 12 V; VSD = 2 V | 6 | ||
| Turn-off time | tOFF | 2 | µs | VCC = 12 V; VSD = 0.8 V | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 30.3 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 33.5 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 17.5 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 0.9 | °C/W | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good-quality, low | 20 |
CAD (KiCad official)
- Symbol:
TPA3111D1PWP - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
tpa3111d1pwp-etched.step/tpa3111d1pwp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpa3111d1pwp.step/tpa3111d1pwp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
5e5c050af5c89735, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).