TPA3110D2QPWPRQ1 from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SD	input	Shutdown logic input for the audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL logic levels with compliance to AVCC.
2	FAULT	output	Open-drain output showing short-circuit or DC detect fault status, voltage compliant to AVCC; connect to SD for short-circuit auto-recovery, otherwise cycle PVCC to reset faults.
3	LINP	input	Positive audio input for left channel, biased at 3 V.
4	LINN	input	Negative audio input for left channel, biased at 3 V.
5	GAIN0	input	Gain select least significant bit, TTL logic levels with compliance to AVCC.
6	GAIN1	input	Gain select most significant bit, TTL logic levels with compliance to AVCC.
7	AVCC	power_in	Analog supply, 8 V to 26 V recommended operating range.
8	AGND	power_in	Analog signal ground, connect to the thermal pad.
9	GVDD	power_out	High-side FET gate drive supply, nominal 7 V, also used as supply for the PLIMIT function; add a 1 uF capacitor to ground.
10	PLIMIT	input	Power limit level adjust: connect a resistor divider from GVDD to GND to set the limit, or connect directly to GVDD for no power limit.
11	RINN	input	Negative audio input for right channel, biased at 3 V.
12	RINP	input	Positive audio input for right channel, biased at 3 V.
13	NC	unconnected	Not connected.
14	PBTL	input	Parallel BTL mode switch (high = PBTL mode, low = BTL mode).
15	PVCCR	power_in	Power supply for right channel H-bridge; right and left channel power supply inputs are connected internally.
16	PVCCR	power_in	Power supply for right channel H-bridge; right and left channel power supply inputs are connected internally.
17	BSPR	passive	Bootstrap I/O for right channel, positive high-side FET.
18	OUTPR	output	Class-D H-bridge positive output for right channel.
19	PGND	power_in	Power ground for the H-bridges.
20	OUTNR	output	Class-D H-bridge negative output for right channel.
21	BSNR	passive	Bootstrap I/O for right channel, negative high-side FET.
22	BSNL	passive	Bootstrap I/O for left channel, negative high-side FET.
23	OUTNL	output	Class-D H-bridge negative output for left channel.
24	PGND	power_in	Power ground for the H-bridges.
25	OUTPL	output	Class-D H-bridge positive output for left channel.
26	BSPL	passive	Bootstrap I/O for left channel, positive high-side FET.
27	PVCCL	power_in	Power supply for left channel H-bridge; right and left channel power supply inputs are connected internally.
28	PVCCL	power_in	Power supply for left channel H-bridge; right and left channel power supply inputs are connected internally.
29	PowerPAD	power_in	Exposed thermal pad on the underside, must be connected to a thermally dissipating ground plane (AGND is connected to it).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-28-EP
Category	Interface ICs
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage AVCC, PVCC	VCC	-0.3		30	V	AVCC, PVCC	4
Interface pin voltage	VI	-0.3			V	SD, GAIN0, GAIN1, PBTL, FAULT; max printed as VCC + 0.3 V; VCC + 0.3 V max printed with <10 V/ms slew	4
PLIMIT pin voltage	VI	-0.3			V	PLIMIT; max printed as GVDD + 0.3 V	4
Audio input pin voltage	VI	-0.3		6.3	V	RINN, RINP, LINN, LINP	4
Minimum load resistance (BTL, PVCC > 15 V)	RL	4.8			Ω	BTL: PVCC > 15 V	4
Minimum load resistance (BTL, PVCC ≤ 15 V)	RL	3.2			Ω	BTL: PVCC ≤ 15 V	4
Minimum load resistance (PBTL)	RL	3.2			Ω	PBTL	4
Operating free-air temperature	TA	-40		125	°C	over operating free-air temperature range	4
Operating junction temperature	TJ	-40		150	°C	Operating junction temperature	4
Storage temperature	Tstg	-65		150	°C		4
Supply voltage PVCC, AVCC	VCC	8		26	V	PVCC, AVCC	4
High-level input voltage	VIH	2			V	SD, GAIN0, GAIN1, PBTL	4
Low-level input voltage	VIL			0.8	V	SD, GAIN0, GAIN1, PBTL	4
Low-level output voltage	VOL			0.8	V	FAULT, RPULL-UP = 100k, VCC = 26 V	4
High-level input current	IIH			50	µA	SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V	4
Low-level input current	IIL			5	µA	SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V	4
Operating free-air temperature	TA	-40		125	°C		4
Class-D output offset voltage (measured differentially)	/VOS/		1.5	15	mV	VCC = 24 V, RL = 8 Ω; VI = 0 V, Gain = 36 dB	5
Quiescent supply current	ICC		32	50	mA	VCC = 24 V; SD = 2 V, no load, PVCC = 24 V	5
Quiescent supply current in shutdown mode	ICC(SD)		250	400	µA	VCC = 24 V; SD = 0.8 V, no load, PVCC = 24 V	5
Gain	G	19	20	21	dB	VCC = 24 V; GAIN1 = 0.8 V, GAIN0 = 0.8 V	5
Gain	G	25	26	27	dB	VCC = 24 V; GAIN1 = 0.8 V, GAIN0 = 2 V	5
Gain	G	31	32	33	dB	VCC = 24 V; GAIN1 = 2 V, GAIN0 = 0.8 V	5
Gain	G	35	36	37	dB	VCC = 24 V; GAIN1 = 2 V, GAIN0 = 2 V	5
Gate drive supply	GVDD	6.4	6.9	7.4	V	VCC = 24 V; IGVDD = 100 µA	5
Quiescent supply current	ICC		20	35	mA	VCC = 12 V; SD = 2 V, no load, PVCC = 12 V	5
Output voltage maximum under PLIMIT control	VO	6.75	7.9	8.75	V	VCC = 12 V; V(PLIMIT) = 2 V; VI = 1 VRMS	5
Oscillator frequency	fOSC	250	310	350	kHz		6
Drain-source on-state resistance, high side	rDS(on)		240		mΩ	VCC = 12 V, IO = 500 mA, TJ = 25°C; high side	5
Drain-source on-state resistance, low side	rDS(on)		240		mΩ	VCC = 12 V, IO = 500 mA, TJ = 25°C; low side	5
Turn-on time	ton		14		ms	VCC = 24 V; SD = 2 V	5
Turn-off time	tOFF		2		μs	VCC = 24 V; SD = 0.8 V	5
DC detect time	tDCDET		420		ms	VCC = 24 V; V(RINN) = 6 V, VRINP = 0 V	5
Quiescent supply current in shutdown mode	ICC(SD)		200		µA	VCC = 12 V; SD = 0.8 V, no load, PVCC = 12 V	5
Turn-off time	tOFF		2		μs	VCC = 12 V; SD = 0.8 V	6
Power supply ripple rejection	KSVR		-70		dB	VCC = 24 V; 200 mVPP ripple at 1 kHz, Gain = 20 dB, inputs AC-coupled to AGND	6
Continuous output power	PO		15		W	VCC = 16 V; THD+N = 10%, f = 1 kHz	6
Total harmonic distortion + noise	THD+N		0.1		%	VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power)	6
Output integrated noise	Vn		65		µV	20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB	6
Crosstalk			-100		dB	VO = 1 VRMS, Gain = 20 dB, f = 1 kHz	6
Signal-to-noise ratio	SNR		102		dB	Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted	6
Supply ripple rejection	KSVR		-70		dB	VCC = 12 V; 200 mVPP ripple from 20 Hz-1 kHz, Gain = 20 dB, inputs AC-coupled to AGND	6
Continuous output power	PO		10		W	VCC = 13 V; THD+N = 10%, f = 1 kHz	6
Total harmonic distortion + noise	THD+N		0.06		%	VCC = 12 V; RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)	6
Junction-to-ambient thermal resistance	θJA		30.3		°C/W	PWP (HTSSOP), 28 pins	5
Junction-to-case (top) thermal resistance	θJCtop		33.5		°C/W	PWP (HTSSOP), 28 pins	5
Junction-to-board thermal resistance	θJB		17.5		°C/W	PWP (HTSSOP), 28 pins	5
Junction-to-case (bottom) thermal resistance	θJCbot		0.9		°C/W	PWP (HTSSOP), 28 pins	5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low	25

CAD (KiCad official)

Symbol: TPA3110D2QPWPRQ1
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: tpa3110d2qpwprq1-etched.step / tpa3110d2qpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpa3110d2qpwprq1.step / tpa3110d2qpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (37 pp, sha256 66cc85493dd58c8b, retrieved 2026-11-09, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPA3110D2QPWPRQ1

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