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TPA3110D2PWP

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Texas Instruments Pre-ordered Chips, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPA3110D2PWP

Texas Instruments · Pre-ordered Chips · HTSSOP-28-EP

TPA3110D2PWP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD input Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL logic levels with compliance to AVCC.
2 FAULT output Open drain output showing short circuit or DC detect fault status, voltage compliant to AVCC; connect to SD for short-circuit auto-recovery, otherwise cycle PVCC to reset faults.
3 LINP input Positive audio input for left channel, biased at 3 V.
4 LINN input Negative audio input for left channel, biased at 3 V.
5 GAIN0 input Gain select least significant bit, TTL logic levels with compliance to AVCC.
6 GAIN1 input Gain select most significant bit, TTL logic levels with compliance to AVCC.
7 AVCC power_in Analog supply.
8 AGND power_in Analog signal ground, connect to the thermal pad.
9 GVDD power_out High-side FET gate drive supply, nominal 7 V, also used as supply for the PLIMIT function.
10 PLIMIT input Power limit level adjust: connect a resistor divider from GVDD to GND to set the limit, or connect directly to GVDD for no power limit.
11 RINN input Negative audio input for right channel, biased at 3 V.
12 RINP input Positive audio input for right channel, biased at 3 V.
13 NC unconnected Not connected.
14 PBTL input Parallel BTL mode switch: tie high for PBTL (mono) mode, connect to local ground for normal BTL operation.
15 PVCCR power_in Power supply for right channel H-bridge, connected internally to the left channel supply inputs.
16 PVCCR power_in Power supply for right channel H-bridge, connected internally to the left channel supply inputs.
17 BSPR passive Bootstrap I/O for right channel, positive high-side FET.
18 OUTPR output Class-D H-bridge positive output for right channel.
19 PGND power_in Power ground for the H-bridges.
20 OUTNR output Class-D H-bridge negative output for right channel.
21 BSNR passive Bootstrap I/O for right channel, negative high-side FET.
22 BSNL passive Bootstrap I/O for left channel, negative high-side FET.
23 OUTNL output Class-D H-bridge negative output for left channel.
24 PGND power_in Power ground for the H-bridges.
25 OUTPL output Class-D H-bridge positive output for left channel.
26 BSPL passive Bootstrap I/O for left channel, positive high-side FET.
27 PVCCL power_in Power supply for left channel H-bridge, connected internally to the right channel supply inputs.
28 PVCCL power_in Power supply for left channel H-bridge, connected internally to the right channel supply inputs.
29 PowerPAD power_in Exposed thermal pad (GND) that must be connected to a thermally dissipating plane, and to which AGND is connected, to avoid thermal protection shutdown.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28-EP
Category Interface ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage AVCC, PVCC VCC -0.3 30 V AVCC, PVCC 5
Interface pin voltage SD, GAIN0, GAIN1, PBTL, FAULT VI -0.3 0.3 V SD, GAIN0, GAIN1, PBTL, FAULT; max printed as VCC + 0.3 V; slew < 10 V/ms 5
Interface pin voltage PLIMIT VI -0.3 0.3 V PLIMIT; max printed as GVDD + 0.3 V 5
Interface pin voltage RINN, RINP, LINN, LINP VI -0.3 6.3 V RINN, RINP, LINN, LINP 5
Minimum load resistance BTL RL 4.8 Ω BTL: PVCC > 15 V 5
Minimum load resistance BTL RL 3.2 Ω BTL: PVCC ≤ 15 V 5
Minimum load resistance PBTL RL 3.2 Ω PBTL 5
Operating free-air temperature TA -40 85 °C 5
Operating junction temperature range TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human-body model, ANSI/ESDA/JEDEC JS-001 6
ESD CDM V(ESD) -500 500 V Charged-device model, JESD22-C101 6
Supply voltage VCC 8 26 V PVCC, AVCC 6
High-level input voltage VIH 2 V SD, GAIN0, GAIN1, PBTL 6
Low-level input voltage VIL 0.8 V SD, GAIN0, GAIN1, PBTL 6
Low-level output voltage VOL 0.8 V FAULT, RPULL-UP= 100 k, VCC= 26 V 6
High-level input current IIH 50 µA SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V 6
Low-level input current IIL 5 µA SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 6
Operating free-air temperature TA -40 85 °C 6
Junction-to-ambient thermal resistance RθJA 30.3 °C/W PWP (HTSSOP) 28 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 33.5 °C/W 6
Junction-to-board thermal resistance RθJB 17.5 °C/W 6
Junction-to-top characterization parameter ψJT 0.9 °C/W 6
Junction-to-board characterization parameter ψJB 7.2 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 0.9 °C/W 6
Class-D output offset voltage (24 V) /VOS/ 1.5 15 mV VI = 0 V, Gain = 36 dB; TA=25°C, VCC=24 V, RL=8 Ω 6
Quiescent supply current (24 V) ICC 32 50 mA SD = 2 V, no load, PVCC = 24 V 6
Quiescent supply current in shutdown (24 V) ICC(SD) 250 400 µA SD = 0.8 V, no load, PVCC = 24 V 6
Drain-source on-state resistance high side rDS(on) 240 mΩ VCC = 12 V, IO = 500 mA, TJ = 25°C, High Side 6
Drain-source on-state resistance low side rDS(on) 240 mΩ VCC = 12 V, IO = 500 mA, TJ = 25°C, Low side 6
Gain (24 V) G 19 20 21 dB GAIN1 = 0.8 V, GAIN0 = 0.8 V 6
Gain (24 V) G 25 26 27 dB GAIN1 = 0.8 V, GAIN0 = 2 V 6
Gain (24 V) G 31 32 33 dB GAIN1 = 2 V, GAIN0 = 0.8 V 6
Gain (24 V) G 35 36 37 dB GAIN1 = 2 V, GAIN0 = 2 V 6
Turn-on time ton 14 ms SD = 2 V 6
Turn-off time tOFF 2 μs SD = 0.8 V 6
Gate Drive Supply (24 V) GVDD 6.4 6.9 7.4 V IGVDD = 100 μA 6
DC Detect time tDCDET 420 ms V(RINN) = 6 V, VRINP = 0 V 6
Class-D output offset voltage (12 V) /VOS/ 1.5 15 mV VI = 0 V, Gain = 36 dB; TA=25°C, VCC=12 V, RL=8 Ω 7
Quiescent supply current (12 V) ICC 20 35 mA SD = 2 V, no load, PVCC = 12V 7
Quiescent supply current in shutdown (12 V) ICC(SD) 200 µA SD = 0.8 V, no load, PVCC = 12V 7
Gate Drive Supply (12 V) GVDD 6.4 6.9 7.4 V IGVDD = 2 mA 7
Output voltage maximum under PLIMIT control VO 6.75 7.9 8.75 V V(PLIMIT) = 2 V; VI = 1 V rms 7
Power supply ripple rejection (24 V) KSVR -70 dB 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND 7
Continuous output power (24 V table) PO 15 W THD+N = 10%, f = 1 kHz, VCC = 16 V 7
Total harmonic distortion + noise (24 V table) THD+N 0.1 % VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) 7
Output integrated noise Vn 65 µV 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 7
Crosstalk (24 V table) Crosstalk -100 dB VO = 1 Vrms, Gain = 20 dB, f = 1 kHz 7
Signal-to-noise ratio SNR 102 dB Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted 7
Oscillator frequency fOSC 250 310 350 kHz 7
Thermal trip point 150 °C 7
Thermal hysteresis 15 °C 7
Supply ripple rejection (12 V) KSVR -70 dB 200 mVPP ripple from 20 Hz-1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND 7
Continuous output power (12 V table) PO 10 W THD+N = 10%, f = 1 kHz; VCC = 13 V 7
Total harmonic distortion + noise (12 V table) THD+N 0.06 % RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power) 7
Crosstalk (12 V table) Crosstalk -100 dB Po = 1 W, Gain = 20 dB, f = 1 kHz 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper 25

CAD (KiCad official)

  • Symbol: TPA3110D2PWP
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: tpa3110d2pwp-etched.step / tpa3110d2pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpa3110d2pwp.step / tpa3110d2pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 065211f4befd1734, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF