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TPA3101D2RGZR
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Texas Instruments Audio Amplifiers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# TPA3101D2RGZR++**Texas Instruments** · Audio Amplifiers · VQFN-48-EP(7x7)++TPA3101D2RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | Not internally connected; the GND row also lists pin 1 for connection to the thermal pad, so this assignment needs verification. |+| 2 | RINN | input | Negative audio input for right channel, biased at VREG/2. |+| 3 | RINP | input | Positive audio input for right channel, biased at VREG/2. |+| 4 | AGND | power_in | Analog ground for digital/analog cells in core; connect to AGND and PGND as a star point for both grounds. |+| 5 | LINP | input | Positive audio input for left channel, biased at VREG/2. |+| 6 | LINN | input | Negative audio input for left channel, biased at VREG/2. |+| 7 | NC | unconnected | Not internally connected. |+| 8 | GAIN0 | input | Gain select least significant bit; TTL logic levels with compliance to VREG. |+| 9 | GAIN1 | input | Gain select most significant bit; TTL logic levels with compliance to VREG. |+| 10 | MSTR/SLV | input | Master/slave select for SYNC direction: HIGH = master mode (SYNC is output), LOW = slave mode (SYNC accepts clock input); TTL logic levels with compliance to VREG. |+| 11 | SYNC | bidirectional | Clock input/output for synchronizing multiple class-D devices; direction set by MSTR/SLV and input signal must not exceed VREG. |+| 12 | NC | unconnected | Not internally connected; the GND row also lists pin 12 for connection to the thermal pad, so this assignment needs verification. |+| 13 | NC | unconnected | Not internally connected; the GND row also lists pin 13 for connection to the thermal pad, so this assignment needs verification. |+| 14 | ROSC | bidirectional | I/O for current-setting resistor of the ramp generator. |+| 15 | VREG | output | 4-V regulated output for internal cells, GAINx, MUTE and MSTR/SLV pins only; not specified for driving other external circuitry. |+| 16 | VBYP | output | Reference for preamplifier, nominally 1.25 V; also controls start-up time via external capacitor sizing. |+| 17 | AGND | power_in | Analog ground for digital/analog cells in core; connect to AGND and PGND as a star point for both grounds. |+| 18 | BSLP | bidirectional | Bootstrap I/O for left channel, positive high-side FET. |+| 19 | LOUTP | output | Class-D 1/2-H-bridge positive output for left channel. |+| 20 | LOUTP | output | Class-D 1/2-H-bridge positive output for left channel. |+| 21 | LOUTN | output | Class-D 1/2-H-bridge negative output for left channel. |+| 22 | LOUTN | output | Class-D 1/2-H-bridge negative output for left channel. |+| 23 | BSLN | bidirectional | Bootstrap I/O for left channel, negative high-side FET. |+| 24 | NC | unconnected | Not internally connected; the GND row also lists pin 24 for connection to the thermal pad, so this assignment needs verification. |+| 25 | NC | unconnected | Not internally connected; the GND row also lists pin 25 for connection to the thermal pad, so this assignment needs verification. |+| 26 | PVCCL | power_in | Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. |+| 27 | PVCCL | power_in | Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. |+| 28 | PGNDL | power_in | Power ground for left channel H-bridge. |+| 29 | PGNDL | power_in | Power ground for left channel H-bridge. |+| 30 | VCLAMPL | power_out | Internally generated voltage supply for left channel bootstrap capacitor. |+| 31 | VCLAMPR | power_out | Internally generated voltage supply for right channel bootstrap capacitor. |+| 32 | PGNDR | power_in | Power ground for right channel H-bridge. |+| 33 | PGNDR | power_in | Power ground for right channel H-bridge. |+| 34 | PVCCR | power_in | Power supply for right channel H-bridge, not connected to PVCCL or AVCC. |+| 35 | PVCCR | power_in | Power supply for right channel H-bridge, not connected to PVCCL or AVCC. |+| 36 | NC | unconnected | Not internally connected; the GND row also lists pin 36 for connection to the thermal pad, so this assignment needs verification. |+| 37 | NC | unconnected | Not internally connected; the GND row also lists pin 37 for connection to the thermal pad, so this assignment needs verification. |+| 38 | BSRN | bidirectional | Bootstrap I/O for right channel, negative high-side FET. |+| 39 | ROUTN | output | Class-D 1/2-H-bridge negative output for right channel. |+| 40 | ROUTN | output | Class-D 1/2-H-bridge negative output for right channel. |+| 41 | ROUTP | output | Class-D 1/2-H-bridge positive output for right channel. |+| 42 | ROUTP | output | Class-D 1/2-H-bridge positive output for right channel. |+| 43 | BSRP | bidirectional | Bootstrap I/O for right channel, positive high-side FET. |+| 44 | SHUTDOWN | input | Shutdown signal for IC (LOW = disabled, HIGH = operational); TTL logic levels with compliance to AVCC. |+| 45 | MUTE | input | Mute for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled); TTL logic levels with compliance to AVCC. |+| 46 | FAULT | output | TTL-compatible short-circuit fault flag (HIGH = short-circuit fault, LOW = no fault); thermal faults are not reported on this terminal. |+| 47 | NC | unconnected | Not internally connected. |+| 48 | AVCC | power_in | High-voltage analog power supply, not internally connected to PVCCR or PVCCL. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Amplifiers/Comparators |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `TPA3101D2RGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `tpa3101d2rgzr-etched.step` / `tpa3101d2rgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpa3101d2rgzr.step` / `tpa3101d2rgzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tpa3101d2) (46 pp, sha256 `883db75757419877`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tpa3101d2rgzr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "amplifiers-comparators",+ "tpa3101d2rgzr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tpa3101d2rgzr.kicad_sym",+ "tpa3101d2rgzr.kicad_mod",+ "tpa3101d2rgzr.glb",+ "tpa3101d2rgzr.step",+ "tpa3101d2rgzr.lbr",+ "docs/hero.png",+ "docs/tpa3101d2rgzr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tpa3101d2rgzr-hero.glb",+ "tpa3101d2rgzr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPA3101D2RGZR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Amplifiers/Comparators",+ "subcategory": "Audio Amplifiers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tpa3101d2",+ "parts": {+ "symbol": "tpa3101d2rgzr.kicad_sym",+ "footprint": "tpa3101d2rgzr.kicad_mod",+ "model_3d": "tpa3101d2rgzr-hero.glb",+ "model_3d_plain": "tpa3101d2rgzr.glb",+ "model_3d_step": "tpa3101d2rgzr-etched.step",+ "model_3d_step_plain": "tpa3101d2rgzr.step",+ "lbr": "tpa3101d2rgzr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2870751",+ "digikey": "296-19424-2-ND",+ "mouser": "595-TPA3101D2RGZR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:54:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-19424-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPA3101D2RGZR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 1 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "2",+ "name": "RINN",+ "type": "input",+ "description": "Negative audio input for right channel, biased at VREG/2."+ },+ {+ "number": "3",+ "name": "RINP",+ "type": "input",+ "description": "Positive audio input for right channel, biased at VREG/2."+ },+ {+ "number": "4",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground for digital/analog cells in core; connect to AGND and PGND as a star point for both grounds."+ },+ {+ "number": "5",+ "name": "LINP",+ "type": "input",+ "description": "Positive audio input for left channel, biased at VREG/2."+ },+ {+ "number": "6",+ "name": "LINN",+ "type": "input",+ "description": "Negative audio input for left channel, biased at VREG/2."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected."+ },+ {+ "number": "8",+ "name": "GAIN0",+ "type": "input",+ "description": "Gain select least significant bit; TTL logic levels with compliance to VREG."+ },+ {+ "number": "9",+ "name": "GAIN1",+ "type": "input",+ "description": "Gain select most significant bit; TTL logic levels with compliance to VREG."+ },+ {+ "number": "10",+ "name": "MSTR/SLV",+ "type": "input",+ "description": "Master/slave select for SYNC direction: HIGH = master mode (SYNC is output), LOW = slave mode (SYNC accepts clock input); TTL logic levels with compliance to VREG."+ },+ {+ "number": "11",+ "name": "SYNC",+ "type": "bidirectional",+ "description": "Clock input/output for synchronizing multiple class-D devices; direction set by MSTR/SLV and input signal must not exceed VREG."+ },+ {+ "number": "12",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 12 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "13",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 13 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "14",+ "name": "ROSC",+ "type": "bidirectional",+ "description": "I/O for current-setting resistor of the ramp generator."+ },+ {+ "number": "15",+ "name": "VREG",+ "type": "output",+ "description": "4-V regulated output for internal cells, GAINx, MUTE and MSTR/SLV pins only; not specified for driving other external circuitry."+ },+ {+ "number": "16",+ "name": "VBYP",+ "type": "output",+ "description": "Reference for preamplifier, nominally 1.25 V; also controls start-up time via external capacitor sizing."+ },+ {+ "number": "17",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground for digital/analog cells in core; connect to AGND and PGND as a star point for both grounds."+ },+ {+ "number": "18",+ "name": "BSLP",+ "type": "bidirectional",+ "description": "Bootstrap I/O for left channel, positive high-side FET."+ },+ {+ "number": "19",+ "name": "LOUTP",+ "type": "output",+ "description": "Class-D 1/2-H-bridge positive output for left channel."+ },+ {+ "number": "20",+ "name": "LOUTP",+ "type": "output",+ "description": "Class-D 1/2-H-bridge positive output for left channel."+ },+ {+ "number": "21",+ "name": "LOUTN",+ "type": "output",+ "description": "Class-D 1/2-H-bridge negative output for left channel."+ },+ {+ "number": "22",+ "name": "LOUTN",+ "type": "output",+ "description": "Class-D 1/2-H-bridge negative output for left channel."+ },+ {+ "number": "23",+ "name": "BSLN",+ "type": "bidirectional",+ "description": "Bootstrap I/O for left channel, negative high-side FET."+ },+ {+ "number": "24",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 24 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "25",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 25 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "26",+ "name": "PVCCL",+ "type": "power_in",+ "description": "Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC."+ },+ {+ "number": "27",+ "name": "PVCCL",+ "type": "power_in",+ "description": "Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC."+ },+ {+ "number": "28",+ "name": "PGNDL",+ "type": "power_in",+ "description": "Power ground for left channel H-bridge."+ },+ {+ "number": "29",+ "name": "PGNDL",+ "type": "power_in",+ "description": "Power ground for left channel H-bridge."+ },+ {+ "number": "30",+ "name": "VCLAMPL",+ "type": "power_out",+ "description": "Internally generated voltage supply for left channel bootstrap capacitor."+ },+ {+ "number": "31",+ "name": "VCLAMPR",+ "type": "power_out",+ "description": "Internally generated voltage supply for right channel bootstrap capacitor."+ },+ {+ "number": "32",+ "name": "PGNDR",+ "type": "power_in",+ "description": "Power ground for right channel H-bridge."+ },+ {+ "number": "33",+ "name": "PGNDR",+ "type": "power_in",+ "description": "Power ground for right channel H-bridge."+ },+ {+ "number": "34",+ "name": "PVCCR",+ "type": "power_in",+ "description": "Power supply for right channel H-bridge, not connected to PVCCL or AVCC."+ },+ {+ "number": "35",+ "name": "PVCCR",+ "type": "power_in",+ "description": "Power supply for right channel H-bridge, not connected to PVCCL or AVCC."+ },+ {+ "number": "36",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 36 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "37",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected; the GND row also lists pin 37 for connection to the thermal pad, so this assignment needs verification."+ },+ {+ "number": "38",+ "name": "BSRN",+ "type": "bidirectional",+ "description": "Bootstrap I/O for right channel, negative high-side FET."+ },+ {+ "number": "39",+ "name": "ROUTN",+ "type": "output",+ "description": "Class-D 1/2-H-bridge negative output for right channel."+ },+ {+ "number": "40",+ "name": "ROUTN",+ "type": "output",+ "description": "Class-D 1/2-H-bridge negative output for right channel."+ },+ {+ "number": "41",+ "name": "ROUTP",+ "type": "output",+ "description": "Class-D 1/2-H-bridge positive output for right channel."+ },+ {+ "number": "42",+ "name": "ROUTP",+ "type": "output",+ "description": "Class-D 1/2-H-bridge positive output for right channel."+ },+ {+ "number": "43",+ "name": "BSRP",+ "type": "bidirectional",+ "description": "Bootstrap I/O for right channel, positive high-side FET."+ },+ {+ "number": "44",+ "name": "SHUTDOWN",+ "type": "input",+ "description": "Shutdown signal for IC (LOW = disabled, HIGH = operational); TTL logic levels with compliance to AVCC."+ },+ {+ "number": "45",+ "name": "MUTE",+ "type": "input",+ "description": "Mute for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled); TTL logic levels with compliance to AVCC."+ },+ {+ "number": "46",+ "name": "FAULT",+ "type": "output",+ "description": "TTL-compatible short-circuit fault flag (HIGH = short-circuit fault, LOW = no fault); thermal faults are not reported on this terminal."+ },+ {+ "number": "47",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected."+ },+ {+ "number": "48",+ "name": "AVCC",+ "type": "power_in",+ "description": "High-voltage analog power supply, not internally connected to PVCCR or PVCCL."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Conflicting assignment: the GND row and the NC row both list pins 1, 12, 13, 24, 25, 36 and 37 in th; Pins 7 and 47 appear only in the NC row, so they are typed as not connected.; The pin-48 description text is garbled in the extraction. The row names AVCC, and the text reads 'no",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0906,+ "at": "2026-10-08T16:53:53"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tpa3101d2",+ "pages": 46,+ "sha256": "883db75757419877",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tpa3101d2rgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tpa3101d2rgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4a52855fc34c204b46c383c1bb6885ac2d1bcf686b621f01e70e7068aef160b9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}