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TPA3101D2RGZR

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Texas Instruments Audio Amplifiers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPA3101D2RGZR

Texas Instruments · Audio Amplifiers · VQFN-48-EP(7x7)

TPA3101D2RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not internally connected; the GND row also lists pin 1 for connection to the thermal pad, so this assignment needs verification.
2 RINN input Negative audio input for right channel, biased at VREG/2.
3 RINP input Positive audio input for right channel, biased at VREG/2.
4 AGND power_in Analog ground for digital/analog cells in core; connect to AGND and PGND as a star point for both grounds.
5 LINP input Positive audio input for left channel, biased at VREG/2.
6 LINN input Negative audio input for left channel, biased at VREG/2.
7 NC unconnected Not internally connected.
8 GAIN0 input Gain select least significant bit; TTL logic levels with compliance to VREG.
9 GAIN1 input Gain select most significant bit; TTL logic levels with compliance to VREG.
10 MSTR/SLV input Master/slave select for SYNC direction: HIGH = master mode (SYNC is output), LOW = slave mode (SYNC accepts clock input); TTL logic levels with compliance to VREG.
11 SYNC bidirectional Clock input/output for synchronizing multiple class-D devices; direction set by MSTR/SLV and input signal must not exceed VREG.
12 NC unconnected Not internally connected; the GND row also lists pin 12 for connection to the thermal pad, so this assignment needs verification.
13 NC unconnected Not internally connected; the GND row also lists pin 13 for connection to the thermal pad, so this assignment needs verification.
14 ROSC bidirectional I/O for current-setting resistor of the ramp generator.
15 VREG output 4-V regulated output for internal cells, GAINx, MUTE and MSTR/SLV pins only; not specified for driving other external circuitry.
16 VBYP output Reference for preamplifier, nominally 1.25 V; also controls start-up time via external capacitor sizing.
17 AGND power_in Analog ground for digital/analog cells in core; connect to AGND and PGND as a star point for both grounds.
18 BSLP bidirectional Bootstrap I/O for left channel, positive high-side FET.
19 LOUTP output Class-D 1/2-H-bridge positive output for left channel.
20 LOUTP output Class-D 1/2-H-bridge positive output for left channel.
21 LOUTN output Class-D 1/2-H-bridge negative output for left channel.
22 LOUTN output Class-D 1/2-H-bridge negative output for left channel.
23 BSLN bidirectional Bootstrap I/O for left channel, negative high-side FET.
24 NC unconnected Not internally connected; the GND row also lists pin 24 for connection to the thermal pad, so this assignment needs verification.
25 NC unconnected Not internally connected; the GND row also lists pin 25 for connection to the thermal pad, so this assignment needs verification.
26 PVCCL power_in Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
27 PVCCL power_in Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
28 PGNDL power_in Power ground for left channel H-bridge.
29 PGNDL power_in Power ground for left channel H-bridge.
30 VCLAMPL power_out Internally generated voltage supply for left channel bootstrap capacitor.
31 VCLAMPR power_out Internally generated voltage supply for right channel bootstrap capacitor.
32 PGNDR power_in Power ground for right channel H-bridge.
33 PGNDR power_in Power ground for right channel H-bridge.
34 PVCCR power_in Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
35 PVCCR power_in Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
36 NC unconnected Not internally connected; the GND row also lists pin 36 for connection to the thermal pad, so this assignment needs verification.
37 NC unconnected Not internally connected; the GND row also lists pin 37 for connection to the thermal pad, so this assignment needs verification.
38 BSRN bidirectional Bootstrap I/O for right channel, negative high-side FET.
39 ROUTN output Class-D 1/2-H-bridge negative output for right channel.
40 ROUTN output Class-D 1/2-H-bridge negative output for right channel.
41 ROUTP output Class-D 1/2-H-bridge positive output for right channel.
42 ROUTP output Class-D 1/2-H-bridge positive output for right channel.
43 BSRP bidirectional Bootstrap I/O for right channel, positive high-side FET.
44 SHUTDOWN input Shutdown signal for IC (LOW = disabled, HIGH = operational); TTL logic levels with compliance to AVCC.
45 MUTE input Mute for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled); TTL logic levels with compliance to AVCC.
46 FAULT output TTL-compatible short-circuit fault flag (HIGH = short-circuit fault, LOW = no fault); thermal faults are not reported on this terminal.
47 NC unconnected Not internally connected.
48 AVCC power_in High-voltage analog power supply, not internally connected to PVCCR or PVCCL.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Amplifiers/Comparators
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Supply voltage PVCC, AVCC VCC -0.3 30 V 2
Input voltage SHUTDOWN, MUTE VI -0.3 V 2
Input voltage GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV, SYNC VI -0.3 V 2
Operating free-air temperature range TA -40 85 °C 2
Operating junction temperature range TJ -40 150 °C 2
Storage temperature range Tstg -65 150 °C 2
Load Resistance R(Load) 3.2 Ω Minimum 2
Electrostatic discharge, human body model -2 2 kV all pins 2
Electrostatic discharge, machine model -200 200 V all pins 2
Electrostatic discharge, charged-device model -500 500 V all pins 2
Supply voltage PVCC, AVCC VCC 10 26 V 2
High-level input voltage SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC VIH 2 V 2
Low-level input voltage SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC VIL 0.8 V 2
High-level input current SHUTDOWN IIH 125 µA VI = VCC, VCC = 24 V 3
High-level input current MUTE IIH 75 µA VI = VCC, VCC = 24 V 3
High-level input current GAIN0, GAIN1, MSTR/SLV, SYNC IIH 2 µA VI = VREG, VCC = 24 V 3
Low-level input current SHUTDOWN IIL 2 µA VI = 0, VCC = 24 V 3
Low-level input current SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV IIL 1 µA VI = 0 V, VCC = 24 V 3
Oscillator frequency fOSC 200 300 kHz Rosc Resistor = 100 kΩ, MSTR/SLV = 2 V 3
Operating free-air temperature range (recommended) TA -40 85 °C 3
Class-D output offset voltage (measured differentially) /VOS/ 5 50 mV VI = 0 V, Gain = 36 dB; VCC = 24 V, RL = 8 Ω, TA = 25°C 3
Bypass reference for input amplifier VBYP 1.1 1.25 1.45 V no load; VCC = 24 V, TA = 25°C 3
4-V internal supply voltage VREG 3.75 4 4.25 V no load, VCC = 10 V to 26 V; VCC = 24 V, TA = 25°C 3
Quiescent supply current ICC 22 26.5 mA SHUTDOWN = 2 V, MUTE = 0 V, no load, filter or snubber; VCC = 24 V 3
Quiescent supply current in shutdown mode ICC(SD) 300 400 µA SHUTDOWN = 0.8 V, no load, filter or snubber; VCC = 24 V 3
Quiescent supply current in mute mode ICC(MUTE) 8 10 mA MUTE = 2 V, no load, filter or snubber; VCC = 24 V 3
Drain-source on-state resistance, total rDS(on) 780 950 mΩ VCC = 12 V, IO = 500 mA, TJ = 25°C 3
Gain G 19 20 21 dB GAIN0 = 0.8 V, GAIN1 = 0.8 V; VCC = 24 V 3
Gain G 25 26 27 dB GAIN0 = 2 V, GAIN1 = 0.8 V; VCC = 24 V 3
Gain G 31 32 33 dB GAIN0 = 0.8 V, GAIN1 = 2 V; VCC = 24 V 3
Gain G 35 36 37 dB GAIN0 = 2 V, GAIN1 = 2 V; VCC = 24 V 3
Quiescent supply current ICC 18 22.5 mA SHUTDOWN = 2 V, MUTE = 0 V, no load, filter or snubber; VCC = 12 V 3
Quiescent supply current in shutdown mode ICC(SD) 180 300 µA SHUTDOWN = 0.8 V, no load, filter or snubber; VCC = 12 V 3
Quiescent supply current in mute mode ICC(MUTE) 7 9 mA MUTE = 2 V, no load, filter or snubber; VCC = 12 V 3
Gain G 19 20 21 dB GAIN0 = 0.8 V, GAIN1 = 0.8 V; VCC = 12 V 4
Gain G 25 26 27 dB GAIN0 = 2 V, GAIN1 = 0.8 V; VCC = 12 V 4
Gain G 31 32 33 dB GAIN0 = 0.8 V, GAIN1 = 2 V; VCC = 12 V 4
Gain G 35 36 37 dB GAIN0 = 2 V, GAIN1 = 2 V; VCC = 12 V 4
Thermal trip point tolerance, device to device -15 15 °C trip point 150 °C 27
Junction-to-ambient thermal resistance qJA 26.4 °C/W RGZ (48 pins) package 2
Junction-to-case (top) thermal resistance qJCtop 19 °C/W RGZ (48 pins) package 2
Junction-to-board thermal resistance qJB 14.4 °C/W RGZ (48 pins) package 2
Junction-to-top characterization parameter yJT 0.2 °C/W RGZ (48 pins) package 2
Junction-to-board characterization parameter yJB 6.3 °C/W RGZ (48 pins) package 2
Junction-to-case (bottom) thermal resistance qJCbot 1.7 °C/W RGZ (48 pins) package 2

CAD (KiCad official)

  • Symbol: TPA3101D2RGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: tpa3101d2rgzr-etched.step / tpa3101d2rgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpa3101d2rgzr.step / tpa3101d2rgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 883db75757419877, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF