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Contents

README

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TPA1286U-SO1R

3PEAK · Instrumentation Amplifiers · SOP-8

TPA1286U-SO1R from 3PEAK, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN- input Inverting/negative differential input; accepts input voltage from (V-) - 0.3V to (V+) + 0.3V with max input bias current ±1.5nA.
2 RG passive Gain-setting resistor connection pin 1; connect external resistor between pins 2 and 8 to set gain from 1 to 1000 using G = 1 + (49.4kΩ/RG).
3 IN+ input Non-inverting/positive differential input; accepts input voltage from (V-) - 0.3V to (V+) + 0.3V with max input bias current ±1.5nA.
4 REF input Reference input with 20kΩ internal impedance; sets DC bias level of output voltage; connect to local ground or offset voltage source.
5 OUT output Amplifier output with rail-to-rail capability; output swing VOH = 0.12V min and VOL = 0.05V min from respective supply rails; short-circuit current ±70mA max.
6 V- power_in Negative power supply; voltage range ±2V to ±18V; add 0.1µF bypass capacitor close to pin.
7 V+ power_in Positive power supply; voltage range ±2V to ±18V; quiescent current 3.8-4.5mA; add 0.1µF bypass capacitor close to pin.
8 RG passive Gain-setting resistor connection pin 2; connect external resistor between pins 2 and 8 to set gain from 1 to 1000 using G = 1 + (49.4kΩ/RG).

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Stage Offset Voltage VOSI -50 10 50 μV At RTI 5
Input Stage Offset Voltage Drift VOSI -0.2 0.1 0.2 μV/°C At RTI, -40°C to 125°C 5
Output Stage Offset Voltage VOSO -300 100 300 μV At RTI 5
Output Stage Offset Voltage Drift VOSO -0.3 0.2 0.3 μV/°C At RTI, -40°C to 125°C 5
Common Mode Rejection Ratio CMRR 80 100 dB CMRR at DC, G=1 5
Common Mode Rejection Ratio CMRR 100 120 dB CMRR at DC, G=10 5
Common Mode Rejection Ratio CMRR 110 130 dB CMRR at DC, G=100 5
Common Mode Rejection Ratio CMRR 120 140 dB CMRR at DC, G=1000 5
Input Bias Current IB 0.3 1.5 nA 5
Input Offset Current IOS 0.3 1.5 nA 5
Power Supply Rejection Ratio PSRR 100 120 dB G=1 5
Power Supply Rejection Ratio PSRR 110 130 dB G=10 5
Power Supply Rejection Ratio PSRR 120 138 dB G=100 5
Power Supply Rejection Ratio PSRR 130 140 dB G=1000 5
Gain G 1 1000 V/V G = 1 + (49.4 kΩ/RG) 5
Gain Error GE -0.05 0.01 0.05 % G=1 5
Gain Error GE -0.15 0.1 0.15 % G=10 5
Gain Error GE -0.2 0.1 0.2 % G=100 5
Gain Error GE -0.6 0.3 0.6 % G=1000 5
Gain vs Temperature G TC 1 5 ppm/°C -40°C to 125°C, G=1 5
Short Circuit Current ISC -70 70 mA -40°C to 125°C 6
Output Swing from Supply Rail (high) VOH 0.12 0.2 V -40°C to 125°C, RL = 10 kΩ 6
Output Swing from Supply Rail (low) VOL 0.05 0.1 V -40°C to 125°C, RL = 10 kΩ 6
Supply Voltage V+ 2 18 V Split supply ±2 V to ±18 V 6
Quiescent Current IQ 3.8 4.5 mA 6
Specified Temperature Range -40 125 °C 6
Supply Voltage 40 V 4
Input Current -10 10 mA IN+, IN- (Note 2) 4
Operating Temperature Range -40 125 °C 4
Maximum Working Junction Temperature 150 °C 4
Storage Temperature Range -65 150 °C 4
Input Voltage Noise Density en 15 nV/√Hz f = 1kHz, G=10 5
Input Voltage Noise (0.1 Hz to 10 Hz) en 1 μV p-p G=1 5
-3dB Bandwidth BW 1600 kHz G=1 6
-3dB Bandwidth BW 400 kHz G=10 6
-3dB Bandwidth BW 100 kHz G=100 6
-3dB Bandwidth BW 11 kHz G=1000 6
Setting Time to 0.01% ST 2.1 μs G=1 6
Slew Rate SR 5 V/μs G=1 6
Slew Rate SR 2.5 V/μs G=100 6
Reference Input Resistance RIN 20 kΩ Reference input 5
Thermal Resistance Junction-to-Ambient, 8-Pin SOP8 θJA 158 °C/W 8-Pin SOP8 4
Thermal Resistance Junction-to-Case, 8-Pin SOP8 θJC 43 °C/W 8-Pin SOP8 4

CAD (KiCad official)

  • Symbol: TPA1286U-SO1R
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tpa1286u-so1r-etched.step / tpa1286u-so1r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpa1286u-so1r.step / tpa1286u-so1r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (20 pp, sha256 075ffb3f5dae61c5, retrieved 2026-10-28, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF