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Contents

README

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TP74LV1T126S5

TECH PUBLIC · Translators, Level Shifters · SOT-23-5

TP74LV1T126S5 from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output-enable control input (active-HIGH); a LOW forces the Y output to high-impedance state.
2 A input Logic signal input; referenced to VCC, supports 1.8 V logic at VCC = 3.3 V for level-shifting.
3 GND power_in Ground reference (0 V).
4 Y tri_state 3-state CMOS output; drives high or low when OE is HIGH, high-impedance when OE is LOW; VOH/VOL referenced to VCC (1.6 V-5.5 V).
5 VCC power_in Supply voltage, operating range 1.6 V to 5.5 V; absolute maximum −0.5 V to 7 V.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-5
Category Logic
Pins 5

CAD (KiCad official)

  • Symbol: TP74LV1T126S5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tp74lv1t126s5-etched.step / tp74lv1t126s5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tp74lv1t126s5.step / tp74lv1t126s5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (8 pp, sha256 dbba2de8596648c1, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF