component
TP5610B
Public Made by Adomby adom
TPOWER DC-DC Converters, ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
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| page.json | 16d ago |
| README.md | 16d ago |
| tp5610b-etched.glb | 16d ago |
| tp5610b-etched.step | 16d ago |
| tp5610b-hero.glb | 16d ago |
| tp5610b-hero.overlay.json | 16d ago |
| tp5610b.glb | 16d ago |
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| tp5610b.step | 16d ago |
TP5610B
TPOWER · DC-DC Converters · ESOP-8
TP5610B from TPOWER, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Supplies the internal high-side power switch driver and connects through a bootstrap capacitor of 68nF to 100nF to the SW pin, which should be placed as close to the chip as possible. |
| 2 | VIN | power_in | Chip supply input with a rated range of -0.3 V to +36 V (absolute maximum), a recommended operating range of 9 V to 30 V, and a input overvoltage protection threshold of 30 V; a bypass capacitor to ground is required. |
| 3 | SW | output | Internal power switch output node that drives the inductor, rated from -0.7 V to VVIN+0.3 V. |
| 4 | PGND | power_in | Chip power ground, which carries the high-current return path of the converter. |
| 5 | GND | power_in | Chip signal ground for the control circuitry, rated for the same -0.3 V to +6 V reference as the other low-voltage pins. |
| 6 | FB | input | Error amplifier feedback input that sets the output voltage through a resistor divider referenced to the 1 V (typical) FB threshold, with R2 recommended below 30 kΩ and a rating of -0.3 V to +6 V. |
| 7 | SNS | input | Output constant-current sense input, where a resistor to ground sets the output current against a 75 mV (typical) reference threshold, with a rating of -0.3 V to +6 V. |
| 8 | EN | input | Chip enable input where logic high (2.5 V minimum) enables switching and logic low (0.6 V maximum) puts the chip in standby, with an internal 200 kΩ pull-up and a rating of -0.3 V to +6 V. |
| 9 | Exposed PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TPOWER |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN input voltage | VVIN | 6.5 | 30 | V | 3 | ||
| EN logic high input voltage | VEN_H | 2.5 | V | 3 | |||
| EN logic low input voltage | VEN_L | 0.6 | V | 3 | |||
| Maximum duty cycle | DMAX | 95 | % | 3 | |||
| High-side power MOSFET drain-source breakdown voltage | VBR_DSS_H | 32 | V | VGS=0V, ID=250uA | 3 | ||
| Low-side power MOSFET drain-source breakdown voltage | VBR_DSS_L | 32 | V | VGS=0V, ID=250uA | 3 | ||
| High-side power MOSFET drain leakage current | ILEAK_H | 1 | uA | VGS=0V, VDS=30V | 3 | ||
| Low-side power MOSFET drain leakage current | ILEAK_L | 1 | uA | VGS=0V, VDS=30V | 3 | ||
| Quiescent operating current | IQC | 360 | uA | EN=0V | 3 | ||
| Recommended system input voltage | VIN | 9 | 30 | V | 正常工作 | 3 | |
| Recommended operating ambient temperature | TOP | -20 | 65 | ℃ | 正常工作 | 3 | |
| VIN to GND voltage | -0.3 | 36 | V | 2 | |||
| SW to GND voltage | -0.7 | V | 2 | ||||
| FB, SNS, EN to GND voltage | -0.3 | 6 | V | 2 | |||
| Power dissipation | 2 | W | 2 | ||||
| Storage ambient temperature | -50 | 150 | ℃ | 2 | |||
| Operating junction temperature range | -40 | 150 | ℃ | 2 | |||
| Operating ambient temperature range | -40 | 105 | ℃ | 2 | |||
| ESD HBM | 2000 | V | 2 | ||||
| ESD MM | 200 | V | 2 | ||||
| VIN start-up voltage | VST | 6.5 | V | VVIN上升 | 3 | ||
| VIN undervoltage lockout threshold | VUVLO | 6.1 | V | VVIN下降 | 3 | ||
| VIN overvoltage protection threshold | VVIN_OVP | 30 | V | VVIN上升 | 3 | ||
| EN pull-up resistance | REN_H | 200 | kΩ | 3 | |||
| Constant-current output reference threshold | VREF_SNS | 75 | mV | 3 | |||
| FB feedback reference threshold | VREF_FB | 1 | V | 3 | |||
| Operating frequency | FOSC | 135 | kHz | 3 | |||
| Minimum on-time | TON_MIN | 400 | ns | 3 | |||
| Output overvoltage protection threshold | VOVP | 105 | % | 相对正常带载时的输出电压 | 3 | ||
| Output overcurrent/short-circuit protection threshold | VOCP | 50 | % | 相对正常带载时的输出电压 | 3 | ||
| Output overcurrent/short-circuit protection delay | TOCP | 15 | ms | 3 | |||
| Output overcurrent/short-circuit recovery time | TREC | 200 | ms | 3 | |||
| High-side power MOSFET on-resistance | RON_H | 58 | mΩ | VGS=5V, ID=1A | 3 | ||
| Low-side power MOSFET on-resistance | RON_L | 58 | mΩ | VGS=5V, ID=1A | 3 | ||
| Over-temperature protection threshold | TSD | 150 | ℃ | 3 | |||
| Over-temperature protection hysteresis | THYS | 125 | ℃ | 3 |
CAD (KiCad official)
- Symbol:
TP5610B - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
tp5610b-etched.step/tp5610b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tp5610b.step/tp5610b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TPOWER datasheet (6 pp, sha256
03af83df175a41c8, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).