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docs tp5108e23e-18: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
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package.json Publish 0.2.0 · Ray 1mo ago
page.json tp5108e23e-18: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 19h ago
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tp5108e23e-18-etched.fit.json tp5108e23e-18: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp5108e23e-18-etched.glb tp5108e23e-18: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp5108e23e-18-etched.step tp5108e23e-18: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp5108e23e-18.glb Publish 0.1.0 · Ray 1mo ago
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tp5108e23e-18.step Publish 0.1.0 · Ray 1mo ago

TP5108E23E-18

TECH PUBLIC · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TP5108E23E-18 from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Supply power input. Absolute max 7V. A 1uF input capacitor (CIN) is recommended per the typical application circuit.
2 GND power_in Ground reference for the regulator.
3 CE input Chip Enable input. VCE >= 1.1V enables the regulator; VCE = 0V puts the device into shutdown (<1uA standby current).
4 NC unconnected No connection. Leave floating or tie as convenient for routing.
5 VOUT power_out Regulated voltage output. Fixed 1.8V (±2%) for the -18 option code, up to 500mA typical output current. A 1uF output capacitor (COUT) is recommended.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TP5108E23E-18

CAD (KiCad official)

  • Symbol: TP5108E23E-18
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tp5108e23e-18-etched.step / tp5108e23e-18-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tp5108e23e-18.step / tp5108e23e-18.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tp5108e23e-18.step 85 KB You want the bare part, or you mark your own boards.
tp5108e23e-18-etched.step 2.4 MB You want the part with TP5108E23E-18 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 582 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (5 pp, sha256 8f002ccefbe6d0d8, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF