TP4056EDTR

{
  "schema_version": 1,
  "type": "component",
  "slug": "tp4056edtr",
  "title": "TP4056EDTR",
  "brief": "XBLW TP4056EDTR XBLW Battery Management, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "pmic",
    "tp4056edtr"
  ],
  "component": {
    "mpn": "TP4056EDTR",
    "manufacturer": "XBLW TP4056EDTR XBLW",
    "package": "ESOP-8",
    "pin_count": 9,
    "category": "PMIC",
    "subcategory": "Battery Management",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/e5f98a56063825c2e9998d7fe0e16aca.pdf",
    "parts": {
      "symbol": "tp4056edtr.kicad_sym",
      "footprint": "tp4056edtr.kicad_mod",
      "model_3d": "tp4056edtr-etched.glb",
      "model_3d_plain": "tp4056edtr.glb",
      "model_3d_step": "tp4056edtr-etched.step",
      "model_3d_step_plain": "tp4056edtr.step",
      "lbr": "tp4056edtr.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "TEMP",
        "type": "input",
        "description": "Battery temperature sense input. Connects to the NTC divider on the battery pack; if V(TEMP) is below ~45% Vcc or above ~80% Vcc the charge cycle is suspended. Tie to GND to disable temperature qualification."
      },
      {
        "number": "2",
        "name": "PROG",
        "type": "bidirectional",
        "description": "Charge-current program and monitor pin. Connect a resistor RPROG from PROG to GND to set IBAT = 1000 * VPROG / RPROG (±15%); the pin regulates to ~1V in constant-current mode and ~0.1V in trickle mode, and the voltage across RPROG can be measured to monitor actual charge current."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground. Electrically common with the exposed thermal pad on the bottom of the ESOP-8 package, which must be soldered to the PCB ground plane for proper heat dissipation."
      },
      {
        "number": "4",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply input (4.5V typ, 6.0V max; abs-max 7V). Supplies the internal circuitry and the pass PMOS to BAT. When VCC falls within ~30mV of VBAT, TP4056 enters a low-power sleep mode and BAT draws <2uA."
      },
      {
        "number": "5",
        "name": "BAT",
        "type": "power_out",
        "description": "Battery connection. Sources up to ~1A of programmed charge current and regulates the float voltage to 4.2V (±1.5%). BAT leakage is <2uA when the chip is disabled or in sleep mode; abs-max continuous BAT current 1000mA."
      },
      {
        "number": "6",
        "name": "STDBY",
        "type": "output",
        "description": "Open-drain charge-complete indicator (active-low, name is overbarred /STDBY). Pulled low by an internal switch when the charge cycle finishes; high-impedance otherwise. VOL ≤ 0.6V at 5mA sink."
      },
      {
        "number": "7",
        "name": "CHRG",
        "type": "output",
        "description": "Open-drain charge-in-progress indicator (active-low, name is overbarred /CHRG). Pulled low by an internal switch while a charge cycle is active; high-impedance when charging is not in progress. VOL ≤ 0.6V at 5mA sink."
      },
      {
        "number": "8",
        "name": "CE",
        "type": "input",
        "description": "Chip-enable input. Logic-high enables normal charging operation; logic-low disables charging and forces the device into a shutdown state. Compatible with TTL and CMOS logic levels; abs-max -0.3V to 8V."
      },
      {
        "number": "9",
        "name": "EXPOSED PAD",
        "type": "power_in",
        "description": "Exposed thermal pad. Present in the package land pattern; connect it per the manufacturer datasheet thermal recommendation. Added because the footprint carries this pad and the symbol had no pin for it.",
        "source": "derived-from-footprint"
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/e5f98a56063825c2e9998d7fe0e16aca.pdf",
        "pages": 15,
        "sha256": "0ba5d249802ce0d4",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -1.905
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm@sha256:5848244c5e72002e",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "tp4056edtr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.9,
          4.9,
          1.65
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "f1718a42c5ea007e8e2dd672ac39a1bb358ee4849bd53c42e21ce83e0e5df7a9",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tp4056edtr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.9,
          4.9,
          1.65
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "5329a095435713c6feccb5992e03c5a33bc72fc9244cca621f7df51b17c582cf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "XBLW",
      "Package": "ESOP-8",
      "Category": "PMIC",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "tp4056edtr"
  ],
  "discovery_pitch": "TP4056EDTR (XBLW TP4056EDTR XBLW) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tp4056edtr.kicad_sym",
    "tp4056edtr.kicad_mod",
    "tp4056edtr.glb",
    "tp4056edtr.step",
    "tp4056edtr-etched.step",
    "tp4056edtr.lbr",
    "docs/hero.png",
    "docs/tp4056edtr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "variants": [
    {
      "mpn": "TP4056EDTR",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T11:20:13.272Z"
}