TP2104N3-G-P003

{
  "slug": "tp2104n3-g-p003",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech MOSFETs, TO-92-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "tp2104n3-g-p003",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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    "path": "docs/hero.png"
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    "tp2104n3-g-p003.lbr",
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    "viewers/symbol.html",
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    "tp2104n3-g-p003-hero.overlay.json",
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  "component": {
    "mpn": "TP2104N3-G-P003",
    "manufacturer": "Microchip Tech",
    "package": "TO-92-3",
    "pin_count": 3,
    "category": "Transistors/Thyristors",
    "subcategory": "MOSFETs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590912448830787584",
    "parts": {
      "symbol": "tp2104n3-g-p003.kicad_sym",
      "footprint": "tp2104n3-g-p003.kicad_mod",
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      "lbr": "tp2104n3-g-p003.lbr"
    },
    "distributor_links": {
      "lcsc": "C629202",
      "digikey": "150-TP2104N3-G-P003TR-ND",
      "mouser": "689-TP2104N3-G-P003"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T06:54:18Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "150-TP2104N3-G-P003TR-ND",
        "status": "found",
        "lifecycle": "Active"
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      "mouser": {
        "pn": "689-TP2104N3-G-P003",
        "status": "found"
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    },
    "pins": [
      {
        "number": "1",
        "name": "Source",
        "type": "passive",
        "description": "Source terminal of the P-channel enhancement-mode vertical DMOS FET, as listed in the TO-92 pin function table (Table 3-2); the datasheet gives no further limits for this pin."
      },
      {
        "number": "2",
        "name": "Gate",
        "type": "input",
        "description": "Gate terminal that controls the P-channel enhancement-mode DMOS FET; the datasheet gives VGS(th) of -1 V to -2 V and an absolute maximum gate-to-source voltage of ±20 V."
      },
      {
        "number": "3",
        "name": "Drain",
        "type": "passive",
        "description": "Drain terminal of the P-channel enhancement-mode vertical DMOS FET, as listed in the TO-92 pin function table (Table 3-2); the datasheet gives no further limits for this pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The Package Types figure on page 1 labels the TO-92 top view as GATE, SOURCE, DRAIN, which conflicts; The datasheet gives only pin names for the TO-92 package (Table 3-2) and no pin-level electrical lim; Pin type classes (Source and Drain as passive, Gate as input) are assigned by me for KiCad ERC; the "
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        "at": "2026-10-18T06:53:39"
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      "pins": {
        "total": 3,
        "described": 3,
        "cites_pages": true,
        "refuses_to_fabricate": true
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        "extents_mm": [
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}