main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tp2019-3-0yc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json tp2019-3-0yc5: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 19h ago
README.md tp2019-3-0yc5: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
tp2019-3-0yc5-etched.fit.json tp2019-3-0yc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp2019-3-0yc5-etched.glb tp2019-3-0yc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp2019-3-0yc5-etched.step tp2019-3-0yc5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp2019-3-0yc5.glb Publish 0.1.0 · Ray 1mo ago
tp2019-3-0yc5.kicad_mod Publish 0.1.0 · Ray 1mo ago
tp2019-3-0yc5.kicad_sym Publish 0.1.0 · Ray 1mo ago
tp2019-3-0yc5.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 5 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
tp2019-3-0yc5.step Publish 0.1.0 · Ray 1mo ago

TP2019-3.0YC5

TECH PUBLIC · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SC-70-5

TP2019-3.0YC5 from TECH PUBLIC, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Regulator input supply. Accepts 2.5V to 5.5V. Bypass to GND with a 1uF capacitor for stable operation.
2 GND power_in Ground reference for the regulator.
3 EN input Active-high shutdown/enable input. VIH >= 1.5V enables the regulator; VIL <= 0.3V drops supply current to ~10nA. Tie to IN for always-on operation. Absolute max: -0.3V to VIN.
4 BP passive Reference-noise bypass pin (fixed-voltage version, applies to TP2019-3.0YC5). Connect a low-leakage 0.01uF ceramic capacitor from BP to GND to reduce output noise to ~30uVRMS. On adjustable versions this pin functions as FB (voltage-divider feedback) instead.
5 OUT power_out Regulated 3.0V output. Delivers up to 150mA (250mA for VOUT>2V) in SC70-5 package. Requires 1uF ceramic output capacitor for stability.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SC-70-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TP2019-3.0YC5

CAD (KiCad official)

  • Symbol: TP2019-3.0YC5
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: tp2019-3-0yc5-etched.step / tp2019-3-0yc5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tp2019-3-0yc5.step / tp2019-3-0yc5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (7 pp, sha256 dc62a2f740a4547d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF