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docs tp181c33s5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json tp181c33s5: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
README.md tp181c33s5: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
tp181c33s5-etched.fit.json tp181c33s5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tp181c33s5-etched.glb tp181c33s5: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
tp181c33s5-etched.step tp181c33s5: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
tp181c33s5.glb Publish 0.1.0 · Ray
tp181c33s5.kicad_mod Publish 0.1.0 · Ray
tp181c33s5.kicad_sym Publish 0.1.0 · Ray
tp181c33s5.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
tp181c33s5.step Publish 0.1.0 · Ray

TP181C33S5

TECH PUBLIC · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TP181C33S5 from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Unregulated supply input. Absolute maximum -0.3 V to +20 V; recommended operating range up to 18 V. Bypass to GND with a 1 uF (1-10 uF) ceramic capacitor (X5R/X7R) close to the pin. For VIN > 12 V hot-plug conditions, an electrolytic or tantalum capacitor is recommended to absorb inrush spikes that could otherwise exceed 30 V.
2 GND power_in Device ground reference for the internal voltage reference and control circuitry. Tie directly to the system ground plane.
3 CE input Chip enable (active high). VCEH >= 1.3 V enables the regulator; VCEL <= 0.7 V disables it. Absolute maximum range is GND-0.3 V to VIN+0.3 V. When CE is low (VCE=0V), the output is actively discharged through an internal ~500 Ohm resistor (RDCHG).
4 NC unconnected No internal connection. Leave floating or tie to GND for mechanical stability. Datasheet marks this pin as 未接 (not connected) for the SOT-23-5 package.
5 VOUT power_out Regulated 3.3 V output (min 3.234 V, max 3.366 V at VIN=4.3 V, IOUT=30 mA). Maximum output current 300 mA; short-circuit current limited to ~40 mA (ISHORT) with over-current protection at ~500 mA (ILIMIT). Requires a 1 uF (1-10 uF) X5R/X7R ceramic output capacitor to GND; absolute max range GND-0.3 V to +7 V.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TP181C33S5
  • TP181C33S5S3L
  • TP181C33S5T3
  • TP181C33S5D6

CAD (KiCad official)

  • Symbol: TP181C33S5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tp181c33s5-etched.step / tp181c33s5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tp181c33s5.step / tp181c33s5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (9 pp, sha256 a7941e6e5dad4048, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF