component

TP121C33S3L

Public Made by Adom

by adom

TECH PUBLIC Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tp121c33s3l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers tp121c33s3l: viewers · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
page.json tp121c33s3l: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md tp121c33s3l: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago
tp121c33s3l-etched.fit.json tp121c33s3l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp121c33s3l-etched.glb tp121c33s3l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp121c33s3l-etched.step tp121c33s3l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tp121c33s3l.glb Publish 0.1.0 · Ray 1mo ago
tp121c33s3l.kicad_mod Publish 0.1.0 · Ray 1mo ago
tp121c33s3l.kicad_sym Publish 0.1.0 · Ray 1mo ago
tp121c33s3l.lbr Publish 0.1.0 · Ray 1mo ago
tp121c33s3l.step Publish 0.1.0 · Ray 1mo ago

TP121C33S3L

TECH PUBLIC · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

TP121C33S3L from TECH PUBLIC, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference terminal. Common return for the regulator's internal voltage reference, error amplifier, and pass FET.
2 VOUT power_out Regulated output terminal. Delivers fixed 3.3V (typ) at up to 200mA for the TP121C33; requires a 1µF-10µF ceramic output capacitor to GND. Absolute range: GND-0.3V to VIN+0.3V.
3 VIN power_in Unregulated supply input. Absolute maximum 7.0V; must exceed VOUT by the dropout voltage (typ 70mV @ 30mA, 240mV @ 100mA for the 3.3V option). Bypass with 1µF-10µF ceramic to GND.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-3L
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • TP121C33S3L
  • TP121C33S3LT3

CAD (KiCad official)

  • Symbol: TP121C33S3L
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: tp121c33s3l-etched.step / tp121c33s3l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tp121c33s3l.step / tp121c33s3l.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tp121c33s3l.step 59 KB You want the bare part, or you mark your own boards.
tp121c33s3l-etched.step 2.1 MB You want the part with TP121C33S3L already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 503 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (10 pp, sha256 ef7573dc12a5e429, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF