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TP0620N3-G

Microchip Tech · MOSFETs · TO-92-3

TP0620N3-G from Microchip Tech, in a TO-92-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Source passive Source terminal of the P-channel enhancement-mode vertical DMOS FET.
2 Gate input Gate terminal with high input impedance; absolute maximum gate-to-source voltage is ±20V and threshold is -1V to -2.4V at ID = -1 mA.
3 Drain passive Drain terminal with drain-to-source breakdown voltage of -200V minimum and continuous drain current of -175 mA in TO-92.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TO-92-3
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-to-Source Breakdown Voltage BVDSS -200 V VGS = 0V, ID = -2 mA 2
Gate Threshold Voltage VGS(th) -1 -2.4 V VGS = VDS, ID = -1 mA 2
Change in VGS(th) with Temperature ΔVGS(th) -4.5 mV/°C VGS = VDS, ID = -1 mA (Note 1) 2
Gate Body Leakage Current IGSS -100 nA VGS = ± 20V, VDS = 0V 2
Zero-Gate Voltage Drain Current IDSS -10 µA VGS = 0V, VDS = Maximum rating 2
Zero-Gate Voltage Drain Current (125°C) IDSS -1 mA VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 1) 2
On-State Drain Current ID(ON) -0.25 A VGS = -5V, VDS = -25V 2
On-State Drain Current ID(ON) -0.75 A VGS = -10V, VDS = -25V 2
Static Drain-to-Source On-State Resistance RDS(ON) 9 15 Ω VGS = -5V, ID = -100 mA 2
Static Drain-to-Source On-State Resistance RDS(ON) 7 12 Ω VGS = -10V, ID = -200 mA 2
Change in RDS(ON) with Temperature ΔRDS(ON) 1.7 %/°C VGS = -10V, ID = -200 mA (Note 1) 2
Forward Transconductance GFS 100 150 mmho VDS = -25V, ID = -400 mA 3
Input Capacitance CISS 85 150 pF VGS = 0V, VDS = -25V, f = 1 MHz 3
Common Source Output Capacitance COSS 30 85 pF VGS = 0V, VDS = -25V, f = 1 MHz 3
Reverse Transfer Capacitance CRSS 10 35 pF VGS = 0V, VDS = -25V, f = 1 MHz 3
Turn-On Delay Time td(ON) 10 ns VDD = -25V, ID = -750 mA, RGEN = 25Ω 3
Rise Time tr 15 ns VDD = -25V, ID = -750 mA, RGEN = 25Ω 3
Turn-Off Delay Time td(OFF) 20 ns VDD = -25V, ID = -750 mA, RGEN = 25Ω 3
Fall Time tf 16 ns VDD = -25V, ID = -750 mA, RGEN = 25Ω 3
Diode Forward Voltage Drop VSD -1.8 V VGS = 0V, ISD = -500 mA (Note 1) 3
Reverse Recovery Time trr 300 ns VGS = 0V, ISD = -500 mA 3
Gate-to-Source Voltage -20 20 V 2
Operating Ambient Temperature (abs max) TA -55 150 °C 2
Storage Temperature (abs max) TS -55 150 °C 2
Operating Ambient Temperature TA -55 150 °C 3
Storage Temperature TS -55 150 °C 3
Package Thermal Resistance, 3-lead TO-92 θJA 132 °C/W 3
Continuous Drain Current ID -175 mA 3-lead TO-92, limited by maximum rated TJ 3
Pulsed Drain Current ID(pulsed) -800 mA 3-lead TO-92 3
Power Dissipation PD 1 W TA = 25°C, 3-lead TO-92 3
Continuous Reverse Drain Current IDR -175 mA 3-lead TO-92, limited by maximum rated TJ 3
Pulsed Reverse Drain Current IDRM -800 mA 3-lead TO-92 3

CAD (KiCad official)

  • Symbol: TP0620N3-G
  • Footprint: Package_TO_SOT_THT:TO-92_Inline
  • 3D model: TO-92-3 (KiCad packages3D, STEP)
  • 3D model files: tp0620n3-g-etched.step / tp0620n3-g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tp0620n3-g.step / tp0620n3-g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (14 pp, sha256 acb583d46a78d6c2, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF