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TMUX4052PWRQ1
Public Made by Adomby adom
Texas Instruments Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMUX4052PWRQ1
Texas Instruments · Analog Switches, Multiplexers · TSSOP-16
TMUX4052PWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S0B | bidirectional | Source pin 0 of multiplexer B; bidirectional signal path for input or output signals in range VSS to VDD. |
| 2 | S2B | bidirectional | Source pin 2 of multiplexer B; bidirectional signal path for input or output signals in range VSS to VDD. |
| 3 | DB | bidirectional | Common drain pin of multiplexer B; bidirectional signal path for input or output signals in range VSS to VDD. |
| 4 | S3B | bidirectional | Source pin 3 of multiplexer B; bidirectional signal path for input or output signals in range VSS to VDD. |
| 5 | S1B | bidirectional | Source pin 1 of multiplexer B; bidirectional signal path for input or output signals in range VSS to VDD. |
| 6 | EN | input | Active low enable; when high all switches are off, when low address pins A[1:0] select one of four input channel pairs. |
| 7 | VSS | power_in | Negative supply rail, most negative potential; decouple to GND with 0.1 µF to 10 µF capacitor for reliable operation. |
| 8 | GND | power_in | Ground reference potential (0 V). |
| 9 | A1 | input | Address line 1 for channel selection; 1.8 V logic compatible with VIH ≥ 1.35 V and VIL ≤ 0.8 V per Table 9-2. |
| 10 | A0 | input | Address line 0 for channel selection; 1.8 V logic compatible with VIH ≥ 1.35 V and VIL ≤ 0.8 V per Table 9-2. |
| 11 | S3A | bidirectional | Source pin 3 of multiplexer A; bidirectional signal path for input or output signals in range VSS to VDD. |
| 12 | S0A | bidirectional | Source pin 0 of multiplexer A; bidirectional signal path for input or output signals in range VSS to VDD. |
| 13 | DA | bidirectional | Common drain pin of multiplexer A; bidirectional signal path for input or output signals in range VSS to VDD. |
| 14 | S1A | bidirectional | Source pin 1 of multiplexer A; bidirectional signal path for input or output signals in range VSS to VDD. |
| 15 | S2A | bidirectional | Source pin 2 of multiplexer A; bidirectional signal path for input or output signals in range VSS to VDD. |
| 16 | VDD | power_in | Positive supply rail, 5 V to 24 V maximum; decouple to GND with 0.1 µF to 10 µF capacitor for reliable operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
TMUX4052PWRQ1 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
tmux4052pwrq1-etched.step/tmux4052pwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tmux4052pwrq1.step/tmux4052pwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
3d97d3723c217f34, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).