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TMUX1511PWR

Texas Instruments · Analog Switches, Multiplexers · TSSOP-14

TMUX1511PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SEL1 input Select pin 1 controls switch #1 (logic low = OFF, logic high = ON) and has an internal 6MΩ pull-down to GND.
2 S1 bidirectional Source pin 1 can be an input or output.
3 D1 bidirectional Drain pin 1 can be an input or output.
4 SEL2 input Select pin 2 controls switch #2 (logic low = OFF, logic high = ON) and has an internal 6MΩ pull-down to GND.
5 S2 bidirectional Source pin 2 can be an input or output.
6 D2 bidirectional Drain pin 2 can be an input or output.
7 GND power_in Ground (0V) reference.
8 D3 bidirectional Drain pin 3 can be an input or output.
9 S3 bidirectional Source pin 3 can be an input or output.
10 SEL3 input Select pin 3 controls switch #3 (logic low = OFF, logic high = ON) and has an internal 6MΩ pull-down to GND.
11 D4 bidirectional Drain pin 4 can be an input or output.
12 S4 bidirectional Source pin 4 can be an input or output.
13 SEL4 input Select pin 4 controls switch #4 (logic low = OFF, logic high = ON) and has an internal 6MΩ pull-down to GND.
14 VDD power_in Positive power supply, the most positive supply potential; connect a decoupling capacitor of 0.1µF to 10µF between VDD and GND for reliable operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Interface
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD Supply voltage VDD -0.5 6 V 4
Logic control input pin voltage (SEL1, SEL2, SEL3, SEL4) VSEL -0.5 6 V 4
Logic control input pin current (SEL1, SEL2, SEL3, SEL4) ISEL -30 30 mA 4
Source or drain pin voltage VS or VD -0.5 6 V 4
Source and drain pin continuous current (S1 to S4, D1 to D4) IS or ID (CONT) -25 25 mA 4
Storage temperature Tstg -65 150 °C 4
Junction temperature TJ 150 °C 4
Supply voltage VDD 1.5 5.5 V 4
Signal path input/output voltage (source or drain pin) VS or VD 0 V VDD ≥ 1.5V; maximum printed as VDD x 2 4
Signal path input/output voltage (source or drain pin), VDD < 1.5V VS_off or VD_off 0 3.6 V VDD < 1.5V 4
Logic control input voltage (SELx) VSEL 0 5.5 V 4
Ambient temperature TA -40 125 °C 4
Electrostatic discharge, human body model (HBM) V(ESD) -2000 2000 V ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, charged-device model (CDM) V(ESD) -750 750 V JEDEC JESD22-C101 4
Power supply voltage VDD 1.5 5.5 V 6
Supply current IDD 37 70 μA VSEL = 0V, 1.4V or VDD; VS = 0V to 5.5V 6
On-resistance RON 2 4.5 Ω VS = 0V to VDD*2, VS(max) = 5.5V, ISD = 8mA 6
On-resistance match between channels ΔRON 0.07 0.28 Ω VS = VDD, ISD = 8mA 6
On-resistance flatness RON(FLAT) 1 1.8 Ω VS = 0V to VDD, ISD = 8mA 6
Powered-off I/O pin leakage current IPOFF -10 0.01 10 nA VDD = 0V, VS = 0V to 3V, VD = 0V, TA = 25℃ 6
Powered-off I/O pin leakage current IPOFF -2 0.01 2 µA VDD = 0V, VS = 0V to 3.6V, VD = 0V 6
OFF leakage current IS(OFF), ID(OFF) -100 0.03 100 nA Switch off; VD = 0.8VDD / 0.2VDD; VS = 0.2VDD / 0.8VDD 6
ON leakage current ID(ON), IS(ON) -50 0.01 50 nA Switch on; VD = 0.8VDD / 0.2VDD, S pins floating, or VS = 0.8VDD / 0.2VDD, D pins floating 6
Input logic high VIH 1.2 5.5 V 6
Input logic low VIL 0 0.45 V 6
Input high leakage current IIH -2 1 2 μA VSEL = 1.8V, VDD 6
Input low leakage current IIL -2 0.2 2 μA VSEL = 0V 6
Source and drain off capacitance COFF 2.5 4 pF Switch OFF; VS = VDD / 2, VSEL = 0V, f = 1MHz 7
Source and drain on capacitance CON 3.3 6 pF Switch ON; VS = VDD / 2, VSEL = VDD, f = 1MHz 7
Turn-on time (VDD to output) tON(VDD) 20 60 µs VS = 3.6V, VDD rise time = 1us, RL = 200Ω, CL = 15pF 7
Turn-off time (VDD to output) tOFF(VDD) 1.2 4 µs VS = 3.6V, VDD fall time = 1us, RL = 200Ω, CL = 15pF 7
Transition time from control input tTRAN 25 55 ns VDD = 2.5V to 5.5V, VS = VDD, RL = 200Ω, CL = 15pF 7
Transition time from control input tTRAN 50 80 ns VDD < 2.5V, VS = VDD, RL = 200Ω, CL = 15pF 7
Internal pull-down resistor on logic input pins RPD 6 MΩ 6
Logic input capacitance CI 3 pF VSEL = 0V, 1.8V or VDD; f = 1MHz 6
Charge injection QC 2 pC Switch ON; VS = VDD / 2, RS = 0Ω, CL = 100pF 7
Off isolation OISO -90 dB Switch OFF; RL = 50Ω, f = 100kHz 7
Off isolation OISO -75 dB Switch OFF; RL = 50Ω, f = 1MHz 7
Channel to channel crosstalk XTALK -90 dB Switch ON; RL = 50Ω, f = 100kHz 7
Bandwidth BW 3 GHz Switch ON; RL = 50Ω 7
Insertion loss ILOSS -0.12 dB Switch ON; RL = 50Ω, f = 1MHz 7
Inter-channel skew tSK(P) 10 ps 7
Propagation delay tPD 67 ps 7
Junction-to-ambient thermal resistance (PW, 14-pin TSSOP) RθJA 129.4 °C/W 4
Junction-to-case (top) thermal resistance (PW, 14-pin TSSOP) RθJC(top) 58.8 °C/W 4
Junction-to-board thermal resistance (PW, 14-pin TSSOP) RθJB 72.4 °C/W 4
Junction-to-top characterization parameter (PW, 14-pin TSSOP) ΨJT 11.6 °C/W 4
Junction-to-board characterization parameter (PW, 14-pin TSSOP) ΨJB 71.9 °C/W 4

CAD (KiCad official)

  • Symbol: TMUX1511PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: tmux1511pwr-etched.step / tmux1511pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tmux1511pwr.step / tmux1511pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 04291b41a68347fe, retrieved 2026-10-19, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF