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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS5702135DPGEQQ1

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

TMS5702135DPGEQQ1 from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FRAYTX2	output	FlexRay data transmit (channel 2) output.
2	FRAYRX2	input	FlexRay data receive (channel 2) input with a fixed 100 uA pull-up.
3	MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]	bidirectional	I2C serial clock, or MibSPI3 chip select 3, or N2HET1[29], or GPIO, with a programmable 20 uA pull-up.
4	MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]	bidirectional	I2C serial data, or MibSPI3 chip select 2, or N2HET1[27], or GPIO, with a programmable 20 uA pull-up.
5	FRAYTXEN2	output	FlexRay transmit enable output (channel 2).
6	N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]	bidirectional	N2HET1[11] or N2HET2[18] time input capture or output compare, or MibSPI3 chip select 4, or GIO, with a programmable 20 uA pull-down and a suppression filter that ignores input pulses shorter than a programmable duration.
7	FLTP1	unconnected	Flash test pad reserved for TI use only; it must connect only to a test pad or be left unconnected (NC).
8	FLTP2	unconnected	Flash test pad reserved for TI use only; it must connect only to a test pad or be left unconnected (NC).
9	GIOA[2]/N2HET2[0]	bidirectional	General-purpose I/O capable of generating CPU interrupts on rising, falling or both edges, or N2HET2[0] time input/output, with a programmable 20 uA pull-down.
10	VCCIO	power_in	Operating supply for I/Os, 3.3 V nominal (recommended 3.0 V to 3.6 V).
11	VSS	power_in	Ground reference for all supplies except VCCAD.
12	CAN3RX	bidirectional	CAN3 receive, or GPIO, with a programmable 20 uA pull-up.
13	CAN3TX	bidirectional	CAN3 transmit, or GPIO.
14	GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS	bidirectional	GPIO, or external clock input #1 (EXTCLKIN), or N2HET1 pin disable, with a programmable 20 uA pull-down.
15	N2HET1[22]	bidirectional	N2HET1[22] time input capture or output compare, or GIO, with a programmable 20 uA pull-down.
16	GIOA[6]/N2HET2[4]	bidirectional	General-purpose I/O capable of generating CPU interrupts on rising, falling or both edges, or N2HET2[4] time input/output, with a programmable 20 uA pull-down.
17	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
18	OSCIN	input	Input from an external crystal/resonator or external clock input.
19	KELVIN_GND	input	Kelvin ground for the oscillator.
20	OSCOUT	output	Output to an external crystal/resonator.
21	VSS	power_in	Ground reference for all supplies except VCCAD.
22	GIOA[7]/N2HET2[6]	bidirectional	General-purpose I/O capable of generating CPU interrupts on rising, falling or both edges, or N2HET2[6] time input/output, with a programmable 20 uA pull-down.
23	N2HET1[1]/SPI4NENA/N2HET2[8]	bidirectional	N2HET1[1] or N2HET2[8] time input capture or output compare, or SPI4 enable, or GIO, with a programmable 20 uA pull-down.
24	N2HET1[3]/SPI4NCS[0]/N2HET2[10]	bidirectional	N2HET1[3] or N2HET2[10] time input capture or output compare, or SPI4 chip select 0, or GIO, with a programmable 20 uA pull-down.
25	N2HET1[0]/SPI4CLK	bidirectional	N2HET1[0] time input capture or output compare, or SPI4 clock, or GIO, with a programmable 20 uA pull-down.
26	VCCIO	power_in	Operating supply for I/Os, 3.3 V nominal (recommended 3.0 V to 3.6 V).
27	VSS	power_in	Ground reference for all supplies except VCCAD.
28	VSS	power_in	Ground reference for all supplies except VCCAD.
29	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
30	N2HET1[2]/SPI4SIMO[0]	bidirectional	N2HET1[2] time input capture or output compare, or SPI4 slave-input master-output, or GIO, with a programmable 20 uA pull-down.
31	N2HET1[5]/SPI4SOMI[0]/N2HET2[12]	bidirectional	N2HET1[5] or N2HET2[12] time input capture or output compare, or SPI4 slave-output master-input, or GIO, with a programmable 20 uA pull-down.
32	MIBSPI5NCS[0]	bidirectional	MibSPI5 chip select 0, or GPIO.
33	N2HET1[7]/N2HET2[14]	bidirectional	N2HET1[7] or N2HET2[14] time input capture or output compare, or GIO, with a suppression filter on input pulses.
34	TEST	bidirectional	Test enable, with a fixed 100 uA pull-down.
35	N2HET1[9]/N2HET2[16]	bidirectional	N2HET1[9] or N2HET2[16] time input capture or output compare, or GIO, with a suppression filter on input pulses.
36	N2HET1[4]	bidirectional	N2HET1[4] time input capture or output compare, or GIO, with a suppression filter on input pulses.
37	MIBSPI3NCS[1]/N2HET1[25]/MDCLK	bidirectional	MibSPI3 chip select 1, or N2HET1[25], or GPIO, with a programmable 20 uA pull-up.
38	N2HET1[6]/SCIRX	bidirectional	SCI receive, or N2HET1[6] time input/output, or GPIO, with a programmable 20 uA pull-down.
39	N2HET1[13]/SCITX	bidirectional	SCI transmit, or N2HET1[13] time input/output, or GPIO, with a programmable 20 uA pull-down.
40	MIBSPI1NCS[2]/N2HET1[19]	bidirectional	MibSPI1 chip select 2, or N2HET1[19], or GPIO, with a programmable 20 uA pull-up.
41	N2HET1[15]/MIBSPI1NCS[4]	bidirectional	N2HET1[15] time input capture or output compare, or MibSPI1 chip select 4, or GPIO.
42	VCCIO	power_in	Operating supply for I/Os, 3.3 V nominal (recommended 3.0 V to 3.6 V).
43	VSS	power_in	Ground reference for all supplies except VCCAD.
44	VSS	power_in	Ground reference for all supplies except VCCAD.
45	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
46	nPORRST	input	Power-on (cold) reset input with a 100 uA pull-down and a glitch filter; the external supply monitor must drive it low when any supply falls out of the specified range.
47	VSS	power_in	Ground reference for all supplies except VCCAD.
48	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
49	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
50	VSS	power_in	Ground reference for all supplies except VCCAD.
51	MIBSPI3SOMI[0]	bidirectional	MibSPI3 slave-output master-input, or GPIO.
52	MIBSPI3SIMO[0]	bidirectional	MibSPI3 slave-input master-output, or GPIO.
53	MIBSPI3CLK	bidirectional	MibSPI3 clock, or GPIO, with a programmable 20 uA pull-up.
54	MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]	bidirectional	MibSPI3 enable or chip select 5, or N2HET1[31], or GPIO, with a programmable 20 uA pull-up.
55	MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS	bidirectional	MibSPI3 chip select 0, or ADC2 event trigger input, or GPIO (GIOB[2]), or N2HET2 pin disable, with a programmable 20 uA pull-up.
56	VSS	power_in	Ground reference for all supplies except VCCAD.
57	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
58	AD1IN[16]/AD2IN[0]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
59	AD1IN[17]/AD2IN[1]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
60	AD1IN[0]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
61	AD1IN[7]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
62	AD1IN[18]/AD2IN[2]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
63	AD1IN[19]/AD2IN[3]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
64	AD1IN[20]/AD2IN[4]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
65	AD1IN[21]/AD2IN[5]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
66	ADREFHI	input	ADC high-voltage reference supply; must lie between VSSAD and VCCAD (common to both ADC cores).
67	ADREFLO	input	ADC low-voltage reference supply; must lie between VSSAD and VCCAD (common to both ADC cores).
68	VSSAD	power_in	ADC supply ground; recommended -0.1 V to 0.1 V with respect to VSS.
69	VCCAD	power_in	Operating supply for the ADC, 3.0 V to 5.25 V (3.3 V or 5.0 V nominal).
70	AD1IN[9]/AD2IN[9]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
71	AD1IN[1]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
72	AD1IN[10]/AD2IN[10]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
73	AD1IN[2]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
74	AD1IN[3]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
75	AD1IN[11]/AD2IN[11]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
76	AD1IN[4]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
77	AD1IN[12]/AD2IN[12]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
78	AD1IN[5]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
79	AD1IN[13]/AD2IN[13]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
80	AD1IN[6]	input	ADC1 analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
81	AD1IN[22]/AD2IN[6]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
82	AD1IN[14]/AD2IN[14]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
83	AD1IN[8]/AD2IN[8]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
84	AD1IN[23]/AD2IN[7]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
85	AD1IN[15]/AD2IN[15]	input	ADC1/ADC2 shared analog input; ADC input pins are rated -0.3 V to 5.5 V (absolute maximum).
86	AD1EVT	bidirectional	ADC1 event trigger input, or GPIO, with a programmable 20 uA pull-down.
87	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
88	VSS	power_in	Ground reference for all supplies except VCCAD.
89	CAN1TX	bidirectional	CAN1 transmit, or GPIO.
90	CAN1RX	bidirectional	CAN1 receive, or GPIO, with a programmable 20 uA pull-up.
91	N2HET1[24]/MIBSPI1NCS[5]	bidirectional	N2HET1[24] time input/output, or MibSPI1 chip select 5, or GPIO, with a programmable 20 uA pull-down.
92	N2HET1[26]	bidirectional	N2HET1[26] time input capture or output compare, or GIO, with a programmable 20 uA pull-down.
93	MIBSPI1SIMO[0]	bidirectional	MibSPI1 slave-input master-output, or GPIO.
94	MIBSPI1SOMI[0]	bidirectional	MibSPI1 slave-output master-input, or GPIO, with a programmable 20 uA pull-up.
95	MIBSPI1CLK	bidirectional	MibSPI1 clock, or GPIO, with a programmable 20 uA pull-up.
96	MIBSPI1NENA/N2HET1[23]	bidirectional	MibSPI1 enable, or N2HET1[23], or GPIO, with a programmable 20 uA pull-up.
97	MIBSPI5NENA	bidirectional	MibSPI5 enable, or GPIO.
98	MIBSPI5SOMI[0]	bidirectional	MibSPI5 slave-output master-input, or GPIO.
99	MIBSPI5SIMO[0]	bidirectional	MibSPI5 slave-input master-output, or GPIO.
100	MIBSPI5CLK	bidirectional	MibSPI5 clock, or GPIO, with a programmable 20 uA pull-up.
101	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
102	VSS	power_in	Ground reference for all supplies except VCCAD.
103	VSS	power_in	Ground reference for all supplies except VCCAD.
104	VCCIO	power_in	Operating supply for I/Os, 3.3 V nominal (recommended 3.0 V to 3.6 V).
105	MIBSPI1NCS[0]/MIBSPI1SOMI[1]	bidirectional	MibSPI1 chip select 0 or slave-output master-input 1, or GPIO.
106	N2HET1[8]/MIBSPI1SIMO[1]	bidirectional	N2HET1[8] time input/output, or MibSPI1 slave-input master-output 1, or GPIO, with a programmable 20 uA pull-down.
107	N2HET1[28]	bidirectional	N2HET1[28] time input capture or output compare, or GIO, with a programmable 20 uA pull-down.
108	TMS	bidirectional	JTAG test select, with a programmable pull-up.
109	nTRST	input	JTAG test hardware reset input.
110	TDI	bidirectional	JTAG test data input, with a programmable pull-up.
111	TDO	bidirectional	JTAG test data output, with a programmable pull-down.
112	TCK	input	JTAG test clock input, with a fixed 100 uA pull-down.
113	RTCK	output	JTAG return test clock output.
114	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
115	VSS	power_in	Ground reference for all supplies except VCCAD.
116	nRST	bidirectional	Warm reset, bidirectional, with a 100 uA pull-up and a glitch filter; an external pull-up resistor is recommended to prevent arbitrary external reset.
117	nERROR	bidirectional	ESM error signal indicating an error of high severity, with a programmable 20 uA pull-down.
118	N2HET1[10]	bidirectional	N2HET1[10] time input capture or output compare, or GIO.
119	ECLK	bidirectional	External prescaled clock output, or GIO, with a programmable 20 uA pull-down.
120	VCCIO	power_in	Operating supply for I/Os, 3.3 V nominal (recommended 3.0 V to 3.6 V).
121	VSS	power_in	Ground reference for all supplies except VCCAD.
122	VSS	power_in	Ground reference for all supplies except VCCAD.
123	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
124	N2HET1[12]	bidirectional	N2HET1[12] time input capture or output compare, or GIO.
125	N2HET1[14]	bidirectional	N2HET1[14] time input capture or output compare, or GIO.
126	FRAYRX1	input	FlexRay data receive (channel 1) input with a fixed 100 uA pull-up.
127	N2HET1[30]	bidirectional	N2HET1[30] time input capture or output compare, or GIO, with a programmable 20 uA pull-down.
128	CAN2TX	bidirectional	CAN2 transmit, or GPIO.
129	CAN2RX	bidirectional	CAN2 receive, or GPIO.
130	MIBSPI1NCS[1]/N2HET1[17]	bidirectional	MibSPI1 chip select 1, or N2HET1[17], or GPIO, with a programmable 20 uA pull-up.
131	LINRX	bidirectional	LIN receive, or GPIO, with a programmable 20 uA pull-up.
132	LINTX	bidirectional	LIN transmit, or GPIO.
133	FRAYTX1	output	FlexRay data transmit (channel 1) output.
134	VCCP	power_in	Flash pump supply, 3.3 V nominal (recommended 3.0 V to 3.6 V).
135	VSS	power_in	Ground reference for all supplies except VCCAD.
136	VCCIO	power_in	Operating supply for I/Os, 3.3 V nominal (recommended 3.0 V to 3.6 V).
137	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
138	VSS	power_in	Ground reference for all supplies except VCCAD.
139	N2HET1[16]	bidirectional	N2HET1[16] time input capture or output compare, or GIO.
140	N2HET1[18]	bidirectional	N2HET1[18] time input capture or output compare, or GIO, with a programmable 20 uA pull-down.
141	N2HET1[20]	bidirectional	N2HET1[20] time input capture or output compare, or GIO, with a programmable 20 uA pull-down.
142	FRAYTXEN1	output	FlexRay transmit enable output (channel 1).
143	VCC	power_in	Core supply, 1.2 V nominal (recommended 1.14 V to 1.32 V).
144	VSS	power_in	Ground reference for all supplies except VCCAD.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-144(20x20)
Category	Embedded Processors & Controllers
Pins	144

CAD (KiCad official)

Symbol: TMS5702135DPGEQQ1
Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
3D model files: tms5702135dpgeqq1-etched.step / tms5702135dpgeqq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms5702135dpgeqq1.step / tms5702135dpgeqq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (170 pp, sha256 cd1c6743045b7e18, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF