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TMS5700432BPZQQ1R

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS5700432BPZQQ1R

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-100(14x14)

TMS5700432BPZQQ1R from Texas Instruments, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GIOA[0]/SPI3nCS[3] bidirectional General-purpose I/O (GPIO) terminal that can interrupt the CPU on rising, falling or both edges; default function GIOA[0], alternate SPI3nCS[3] via PINMMR0[9]; default pulldown 20 µA programmable.
2 GIOA[1]/SPI3nCS[2] bidirectional General-purpose I/O (GPIO) with interrupt capability on rising, falling or both edges; alternate function SPI3nCS[2] selected via PINMMR1[1].
3 FLTP1 input Flash test pin; for proper operation it must connect only to a test pad or be left unconnected (NC), and the test pad must not be exposed to ESD in the final product.
4 FLTP2 input Flash test pin; for proper operation it must connect only to a test pad or be left unconnected (NC), and the test pad must not be exposed to ESD in the final product.
5 GIOA[2]/SPI3nCS[1] bidirectional General-purpose I/O (GPIO) with interrupt capability on rising, falling or both edges; alternate function SPI3nCS[1] selected via PINMMR1[9].
6 VCCIO power_in I/O supply, 3.3 V nominal; recommended operating range 3.0 V to 3.6 V.
7 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
8 GIOA[3]/SPI2nCS[3] bidirectional General-purpose I/O (GPIO) with interrupt capability on rising, falling or both edges; alternate function SPI2nCS[3].
9 GIOA[4]/SPI2nCS[2] bidirectional General-purpose I/O (GPIO) with interrupt capability on rising, falling or both edges; alternate function SPI2nCS[2].
10 GIOA[5]/EXTCLKIN bidirectional General-purpose I/O (GPIO) with interrupt capability; alternate function is External Clock In (EXTCLKIN) with 20 µA pulldown.
11 N2HET[22] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
12 GIOA[6]/SPI2nCS[1]/N2HET[31] bidirectional General-purpose I/O (GPIO) with interrupt capability; alternates are SPI2nCS[1] (PINMMR2[9]) and N2HET[31] (PINMMR2[10]).
13 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
14 OSCIN input Input from external crystal/resonator or external clock input for the main oscillator.
15 KELVIN_GND power_in Dedicated ground for the oscillator.
16 OSCOUT output Output to external crystal/resonator for the main oscillator.
17 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
18 GIOA[7]/N2HET[29] bidirectional General-purpose I/O (GPIO) with interrupt capability; alternate function N2HET[29] selected via PINMMR2[17].
19 N2HET[0] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
20 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
21 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
22 N2HET[2] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
23 SPI2nCS[0] bidirectional SPI2 chip select, or GPIO.
24 TEST bidirectional Test enable; must be connected directly to ground or through a pulldown resistor.
25 N2HET[4] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
26 N2HET[6] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
27 MIBSPI1nCS[2]/N2HET[20]/N2HET[19] bidirectional MibSPI1 chip select 2 by default; alternates N2HET[20] (PINMMR3[1]) and N2HET[19] (PINMMR3[2]), or GPIO.
28 VCCIO power_in I/O supply, 3.3 V nominal; recommended operating range 3.0 V to 3.6 V.
29 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
30 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
31 nPORRST input Power-on reset (cold reset); external supply monitor circuitry must drive it low when any microcontroller supply is out of the specified range; has a glitch filter and 100 µA pulldown.
32 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
33 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
34 SPI3SOMI bidirectional SPI3 Slave-Out-Master-In, or GPIO.
35 SPI3SIMO bidirectional SPI3 Slave-In-Master-Out, or GPIO.
36 SPI3CLK/EQEPA bidirectional SPI3 serial clock by default; alternate Enhanced QEP Input A (EQEPA) selected via PINMMR3[17]; 20 µA pullup.
37 SPI3nENA/EQEPB bidirectional SPI3 enable by default; alternate Enhanced QEP Input B (EQEPB) selected via PINMMR3[25].
38 SPI3nCS[0]/EQEPI bidirectional SPI3 chip select 0 by default; alternate Enhanced QEP Index (EQEPI) selected via PINMMR4[1].
39 MIBSPI1nCS[3]/N2HET[26] bidirectional MibSPI1 chip select 3 by default; alternate N2HET[26] selected via PINMMR4[9], or GPIO.
40 ADIN[16] input Analog input channel 16 of the 12-bit multibuffered ADC (MibADC).
41 ADIN[17] input Analog input channel 17 of the 12-bit multibuffered ADC (MibADC).
42 ADIN[0] input Analog input channel 0 of the 12-bit multibuffered ADC (MibADC).
43 ADIN[7] input Analog input channel 7 of the 12-bit multibuffered ADC (MibADC).
44 ADIN[20] input Analog input channel 20 of the 12-bit multibuffered ADC (MibADC).
45 ADIN[21] input Analog input channel 21 of the 12-bit multibuffered ADC (MibADC).
46 VCCAD/ADREFHI power_in MibADC operating supply and high-voltage reference; 3.3 V nominal, recommended range 3.0 V to 3.6 V.
47 VSSAD/ADREFLO power_in MibADC supply ground and low-voltage reference; recommended range -0.1 V to 0.1 V.
48 ADIN[9] input Analog input channel 9 of the 12-bit multibuffered ADC (MibADC).
49 ADIN[1] input Analog input channel 1 of the 12-bit multibuffered ADC (MibADC).
50 ADIN[10] input Analog input channel 10 of the 12-bit multibuffered ADC (MibADC).
51 ADIN[2] input Analog input channel 2 of the 12-bit multibuffered ADC (MibADC).
52 ADIN[3] input Analog input channel 3 of the 12-bit multibuffered ADC (MibADC).
53 ADIN[11] input Analog input channel 11 of the 12-bit multibuffered ADC (MibADC).
54 ADIN[4] input Analog input channel 4 of the 12-bit multibuffered ADC (MibADC).
55 ADIN[5] input Analog input channel 5 of the 12-bit multibuffered ADC (MibADC).
56 ADIN[6] input Analog input channel 6 of the 12-bit multibuffered ADC (MibADC).
57 ADIN[8] input Analog input channel 8 of the 12-bit multibuffered ADC (MibADC).
58 ADEVT/N2HET[28] bidirectional ADC event trigger by default; alternate N2HET[28] selected via PINMMR4[17], or GPIO; 20 µA pullup.
59 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
60 VCCIO power_in I/O supply, 3.3 V nominal; recommended operating range 3.0 V to 3.6 V.
61 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
62 CAN1TX bidirectional DCAN1 CAN transmit, or GPIO.
63 CAN1RX bidirectional DCAN1 CAN receive, or GPIO; 20 µA programmable pullup.
64 N2HET[24] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
65 MIBSPI1SIMO bidirectional MibSPI1 Slave-In-Master-Out, or GPIO.
66 MIBSPI1SOMI bidirectional MibSPI1 Slave-Out-Master-In, or GPIO.
67 MIBSPI1CLK bidirectional MibSPI1 serial clock, or GPIO; 20 µA programmable pullup.
68 MIBSPI1nENA/N2HET[23]/N2HET[30] bidirectional MibSPI1 enable by default; alternates N2HET[23] (PINMMR5[9]) and N2HET[30] (PINMMR5[10]), or GPIO.
69 SPI2SOMI bidirectional SPI2 Slave-Out-Master-In, or GPIO; drive strength selected by the SRS bit in SPIPC9 (8 mA default, 2 mA when SRS=1).
70 SPI2SIMO bidirectional SPI2 Slave-In-Master-Out, or GPIO; drive strength selected by the SRS bit in SPIPC9 (8 mA default, 2 mA when SRS=1).
71 SPI2CLK bidirectional SPI2 serial clock, or GPIO; drive strength selected by the SRS bit in SPIPC9 (8 mA default, 2 mA when SRS=1).
72 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
73 MIBSPI1nCS[0] bidirectional MibSPI1 chip select 0, or GPIO.
74 N2HET[8] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
75 TMS bidirectional JTAG test select, with fixed 100 µA pullup.
76 nTRST input JTAG test hardware reset, with fixed 100 µA pulldown.
77 TDI bidirectional JTAG test data in, with fixed 100 µA pullup.
78 TDO output JTAG test data out, with fixed 100 µA pulldown.
79 TCK input JTAG test clock, with fixed 100 µA pulldown.
80 RTCK output JTAG return test clock.
81 nRST bidirectional External circuitry can assert a system reset by driving it low; an external pullup is recommended; has a glitch filter and 100 µA pullup.
82 nERROR bidirectional ESM error signal indicating a high-severity error; can be monitored externally as an indicator of a fault, with 20 µA pulldown.
83 N2HET[10] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
84 ECLK bidirectional External prescaled clock output (frequency is a user-programmable ratio of VCLK), or GPIO; 20 µA pulldown.
85 VCCIO power_in I/O supply, 3.3 V nominal; recommended operating range 3.0 V to 3.6 V.
86 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
87 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.
88 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
89 N2HET[12] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
90 N2HET[14] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
91 CAN2TX bidirectional DCAN2 CAN transmit, or GPIO.
92 CAN2RX bidirectional DCAN2 CAN receive, or GPIO.
93 MIBSPI1nCS[1]/EQEPS/N2HET[17] bidirectional MibSPI1 chip select 1 by default; alternates Enhanced QEP Strobe (EQEPS, PINMMR6[9]) and N2HET[17] (PINMMR6[10]), or GPIO.
94 LINRX bidirectional LIN receive, or GPIO; 20 µA programmable pullup.
95 LINTX bidirectional LIN transmit, or GPIO.
96 VCCP power_in Flash external pump supply, 3.3 V nominal (3.0 V to 3.6 V); required for flash read, program and erase operations.
97 N2HET[16] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
98 N2HET[18] bidirectional N2HET timer input capture or output compare; can be programmed as GPIO and has a programmable-duration suppression filter.
99 VCC power_in Digital logic and RAM core supply, 1.2 V nominal; recommended operating range 1.14 V to 1.32 V.
100 VSS power_in Device ground reference; single ground for all supplies except the ADC supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS5700432BPZQQ1R
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms5700432bpzqq1r-etched.step / tms5700432bpzqq1r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms5700432bpzqq1r.step / tms5700432bpzqq1r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (114 pp, sha256 5d616069ef21fdcb, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF