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TMS5700432BPZQQ1

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS5700432BPZQQ1

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-100(14x14)

TMS5700432BPZQQ1 from Texas Instruments, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GIOA[0]/SPI3nCS[3] bidirectional General-purpose I/O with interrupt on rising, falling or both edges; alternate function SPI3nCS[3]; default pulldown is programmable at 20 µA.
2 GIOA[1]/SPI3nCS[2] bidirectional General-purpose I/O with interrupt on rising, falling or both edges; alternate function SPI3nCS[2]; default pulldown is programmable at 20 µA.
3 FLTP1 input Flash test pin; for proper operation it must connect only to a test pad or be left unconnected (NC), and the test pad must not be exposed to ESD in the final product.
4 FLTP2 input Flash test pin; for proper operation it must connect only to a test pad or be left unconnected (NC), and the test pad must not be exposed to ESD in the final product.
5 GIOA[2]/SPI3nCS[1] bidirectional General-purpose I/O with interrupt on rising, falling or both edges; alternate function SPI3nCS[1]; default pulldown is programmable at 20 µA.
6 VCCIO power_in I/O supply, 3.3 V nominal (3.0 V to 3.6 V recommended operating range).
7 VSS power_in Device ground reference for all supplies except the ADC supply.
8 GIOA[3]/SPI2nCS[3] bidirectional General-purpose I/O with interrupt on rising, falling or both edges; alternate function SPI2nCS[3]; default pulldown is programmable at 20 µA.
9 GIOA[4]/SPI2nCS[2] bidirectional General-purpose I/O with interrupt on rising, falling or both edges; alternate function SPI2nCS[2]; default pulldown is programmable at 20 µA.
10 GIOA[5]/EXTCLKIN bidirectional General-purpose I/O, or external clock input EXTCLKIN; also connects directly to the N2HET PIN_nDISABLE input when PINMMR9[0] = 1.
11 N2HET[22] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
12 GIOA[6]/SPI2nCS[1]/N2HET[31] bidirectional General-purpose I/O; alternate functions SPI2nCS[1] and N2HET[31]; default pulldown is programmable at 20 µA.
13 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
14 OSCIN input Input from external crystal/resonator or external clock input for the main oscillator.
15 KELVIN_GND power_in Dedicated ground for the oscillator.
16 OSCOUT output Output to external crystal/resonator.
17 VSS power_in Device ground reference for all supplies except the ADC supply.
18 GIOA[7]/N2HET[29] bidirectional General-purpose I/O; alternate function N2HET[29]; the pin is connected as input to both the GPIO and N2HET modules.
19 N2HET[0] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
20 VSS power_in Device ground reference for all supplies except the ADC supply.
21 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
22 N2HET[2] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
23 SPI2nCS[0] bidirectional SPI2 chip select, or GPIO.
24 TEST bidirectional Test enable; this terminal must be connected to ground directly or through a pulldown resistor.
25 N2HET[4] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
26 N2HET[6] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
27 MIBSPI1nCS[2]/N2HET[20]/N2HET[19] bidirectional MibSPI1 chip select 2; alternate functions N2HET[20] and N2HET[19]; or GPIO.
28 VCCIO power_in I/O supply, 3.3 V nominal (3.0 V to 3.6 V recommended operating range).
29 VSS power_in Device ground reference for all supplies except the ADC supply.
30 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
31 nPORRST input Power-on reset (cold reset); external power supply monitor circuitry must drive it low when any microcontroller supply falls out of the specified range, and it has a glitch filter.
32 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
33 VSS power_in Device ground reference for all supplies except the ADC supply.
34 SPI3SOMI bidirectional SPI3 slave-out master-in, or GPIO.
35 SPI3SIMO bidirectional SPI3 slave-in master-out, or GPIO.
36 SPI3CLK/EQEPA bidirectional SPI3 serial clock, or enhanced QEP input A; default pullup is programmable at 20 µA.
37 SPI3nENA/EQEPB bidirectional SPI3 enable, or enhanced QEP input B.
38 SPI3nCS[0]/EQEPI bidirectional SPI3 chip select 0, or enhanced QEP index input.
39 MIBSPI1nCS[3]/N2HET[26] bidirectional MibSPI1 chip select 3, alternate function N2HET[26], or GPIO.
40 ADIN[16] input MibADC analog input channel 16.
41 ADIN[17] input MibADC analog input channel 17.
42 ADIN[0] input MibADC analog input channel 0.
43 ADIN[7] input MibADC analog input channel 7.
44 ADIN[20] input MibADC analog input channel 20.
45 ADIN[21] input MibADC analog input channel 21.
46 VCCAD/ADREFHI power_in MibADC operating supply and high-voltage reference, 3.3 V nominal (3.0 V to 3.6 V).
47 VSSAD/ADREFLO power_in MibADC supply ground and low-voltage reference, -0.1 V to 0.1 V.
48 ADIN[9] input MibADC analog input channel 9.
49 ADIN[1] input MibADC analog input channel 1.
50 ADIN[10] input MibADC analog input channel 10.
51 ADIN[2] input MibADC analog input channel 2.
52 ADIN[3] input MibADC analog input channel 3.
53 ADIN[11] input MibADC analog input channel 11.
54 ADIN[4] input MibADC analog input channel 4.
55 ADIN[5] input MibADC analog input channel 5.
56 ADIN[6] input MibADC analog input channel 6.
57 ADIN[8] input MibADC analog input channel 8.
58 ADEVT/N2HET[28] bidirectional ADC event trigger, alternate function N2HET[28], or GPIO; default pullup is programmable at 20 µA.
59 VSS power_in Device ground reference for all supplies except the ADC supply.
60 VCCIO power_in I/O supply, 3.3 V nominal (3.0 V to 3.6 V recommended operating range).
61 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
62 CAN1TX bidirectional DCAN1 CAN transmit, or GPIO; default pullup is programmable at 20 µA.
63 CAN1RX bidirectional DCAN1 CAN receive, or GPIO; default pullup is programmable at 20 µA.
64 N2HET[24] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
65 MIBSPI1SIMO bidirectional MibSPI1 slave-in master-out, or GPIO.
66 MIBSPI1SOMI bidirectional MibSPI1 slave-out master-in, or GPIO.
67 MIBSPI1CLK bidirectional MibSPI1 serial clock, or GPIO; default pullup is programmable at 20 µA.
68 MIBSPI1nENA/N2HET[23]/N2HET[30] bidirectional MibSPI1 enable; alternate functions N2HET[23] and N2HET[30]; or GPIO.
69 SPI2SOMI bidirectional SPI2 slave-out master-in, or GPIO; drive strength selected by SPIPC9 SRS bit (8 mA fast default, 2 mA slow).
70 SPI2SIMO bidirectional SPI2 slave-in master-out, or GPIO; drive strength selected by SPIPC9 SRS bit (8 mA fast default, 2 mA slow).
71 SPI2CLK bidirectional SPI2 serial clock, or GPIO; drive strength selected by SPIPC9 SRS bit (8 mA fast default, 2 mA slow).
72 VSS power_in Device ground reference for all supplies except the ADC supply.
73 MIBSPI1nCS[0] bidirectional MibSPI1 chip select 0, or GPIO.
74 N2HET[8] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
75 TMS bidirectional JTAG test select; default pullup is fixed at 100 µA.
76 nTRST input JTAG test hardware reset; pulldown is fixed at 100 µA.
77 TDI bidirectional JTAG test data in; default pullup is fixed at 100 µA.
78 TDO output JTAG test data out; default pulldown is fixed at 100 µA.
79 TCK input JTAG test clock; pulldown is fixed at 100 µA.
80 RTCK output JTAG return test clock.
81 nRST bidirectional External circuitry can assert a system reset by driving it low; TI recommends an external pullup, and the terminal has a glitch filter.
82 nERROR bidirectional ESM error signal indicating an error of high severity; default pulldown is 20 µA.
83 N2HET[10] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
84 ECLK bidirectional External prescaled clock output, or GPIO; default pulldown is programmable at 20 µA.
85 VCCIO power_in I/O supply, 3.3 V nominal (3.0 V to 3.6 V recommended operating range).
86 VSS power_in Device ground reference for all supplies except the ADC supply.
87 VSS power_in Device ground reference for all supplies except the ADC supply.
88 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
89 N2HET[12] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
90 N2HET[14] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
91 CAN2TX bidirectional DCAN2 CAN transmit, or GPIO; default pullup is programmable at 20 µA.
92 CAN2RX bidirectional DCAN2 CAN receive, or GPIO; default pullup is programmable at 20 µA.
93 MIBSPI1nCS[1]/EQEPS/N2HET[17] bidirectional MibSPI1 chip select 1; alternate functions EQEPS (enhanced QEP strobe) and N2HET[17]; or GPIO.
94 LINRX bidirectional LIN receive, or GPIO; default pullup is programmable at 20 µA.
95 LINTX bidirectional LIN transmit, or GPIO.
96 VCCP power_in Flash external pump supply, 3.3 V nominal (3.0 V to 3.6 V); required for flash read, program and erase operations.
97 N2HET[16] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
98 N2HET[18] bidirectional N2HET timer input capture or output compare; the terminal can be programmed as GPIO and has a programmable-duration suppression filter.
99 VCC power_in Digital logic and RAM core supply, 1.2 V nominal (1.14 V to 1.32 V recommended operating range).
100 VSS power_in Device ground reference for all supplies except the ADC supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS5700432BPZQQ1
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms5700432bpzqq1-etched.step / tms5700432bpzqq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms5700432bpzqq1.step / tms5700432bpzqq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (114 pp, sha256 5d616069ef21fdcb, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF