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TMS320VC5509APGE
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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+180@@ -0,0 +1,180 @@+# TMS320VC5509APGE++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)++TMS320VC5509APGE from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 2 | PU | output | USB internal pullup enable signal driven by device |+| 3 | DP | input | USB D+ differential signal input to transceiver with series resistor protection |+| 4 | DN | input | USB D- differential signal input to transceiver with series resistor protection |+| 5 | USBVDD | power_in | USB module I/O supply voltage 3.0V-3.6V for DP, DN, and PU pins |+| 6 | GPIO7 | input | General-purpose I/O pin 7, configurable as input or output via IODIR register |+| 7 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 8 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 9 | GPIO2 | input | General-purpose I/O pin 2, configurable as input or output via IODIR register |+| 10 | GPIO1 | input | General-purpose I/O pin 1, configurable as input or output via IODIR register |+| 11 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 12 | GPIO0 | input | General-purpose I/O pin 0 and mode select pin that determines parallel bus function configuration |+| 13 | X2/CLKIN | input | External clock input or crystal oscillator pin 2 accepting clock frequencies 6-20 MHz |+| 14 | X1 | input | Crystal oscillator pin 1 for parallel resonant crystal connection |+| 15 | CLKOUT | output | Clock output from internal DPLL providing system clock or divided reference clock to external circuits |+| 16 | C0 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 17 | C1 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 18 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 19 | C2 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 20 | C3 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 21 | C4 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 22 | C5 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 23 | C6 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 24 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 25 | C7 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 26 | C8 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 27 | C9 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 28 | C11 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 29 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 30 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 31 | C14 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 32 | C12 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 33 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 34 | C10 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 35 | C13 | tri_state | EMIF chip select or multiplexed signal functioning as external memory interface output |+| 36 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 37 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 38 | A13 | tri_state | Address bus bit 13 for external memory interface or general-purpose I/O depending on EBSR setting |+| 39 | A12 | tri_state | Address bus bit 12 for external memory interface or general-purpose I/O depending on EBSR setting |+| 40 | A11 | tri_state | Address bus bit 11 for external memory interface or general-purpose I/O depending on EBSR setting |+| 41 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 42 | A10 | tri_state | Address bus bit 10 for external memory interface or general-purpose I/O depending on EBSR setting |+| 43 | A9 | tri_state | Address bus bit 9 for external memory interface or general-purpose I/O depending on EBSR setting |+| 44 | A8 | tri_state | Address bus bit 8 for external memory interface or general-purpose I/O depending on EBSR setting |+| 45 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 46 | A7 | tri_state | Address bus bit 7 for external memory interface or general-purpose I/O depending on EBSR setting |+| 47 | A6 | tri_state | Address bus bit 6 for external memory interface or general-purpose I/O depending on EBSR setting |+| 48 | A5 | tri_state | Address bus bit 5 for external memory interface or general-purpose I/O depending on EBSR setting |+| 49 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 50 | A4 | tri_state | Address bus bit 4 for external memory interface or general-purpose I/O depending on EBSR setting |+| 51 | A3 | tri_state | Address bus bit 3 for external memory interface or general-purpose I/O depending on EBSR setting |+| 52 | A2 | tri_state | Address bus bit 2 for external memory interface or general-purpose I/O depending on EBSR setting |+| 53 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 54 | A1 | tri_state | Address bus bit 1 for external memory interface or general-purpose I/O depending on EBSR setting |+| 55 | A0 | tri_state | Address bus bit 0 for external memory interface or general-purpose I/O, XORed with A14 on EMIF |+| 56 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 57 | D0 | tri_state | Data bus bit 0 for external memory interface or peripheral communication |+| 58 | D1 | tri_state | Data bus bit 1 for external memory interface or peripheral communication |+| 59 | D2 | tri_state | Data bus bit 2 for external memory interface or peripheral communication |+| 60 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 61 | D3 | tri_state | Data bus bit 3 for external memory interface or peripheral communication |+| 62 | D4 | tri_state | Data bus bit 4 for external memory interface or peripheral communication |+| 63 | D5 | tri_state | Data bus bit 5 for external memory interface or peripheral communication |+| 64 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 65 | D6 | tri_state | Data bus bit 6 for external memory interface or peripheral communication |+| 66 | D7 | tri_state | Data bus bit 7 for external memory interface or peripheral communication |+| 67 | D8 | tri_state | Data bus bit 8 for external memory interface or peripheral communication |+| 68 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 69 | D9 | tri_state | Data bus bit 9 for external memory interface or peripheral communication |+| 70 | D10 | tri_state | Data bus bit 10 for external memory interface or peripheral communication |+| 71 | D11 | tri_state | Data bus bit 11 for external memory interface or peripheral communication |+| 72 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 73 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 74 | D12 | tri_state | Data bus bit 12 for external memory interface or peripheral communication |+| 75 | D13 | tri_state | Data bus bit 13 for external memory interface or peripheral communication |+| 76 | D14 | tri_state | Data bus bit 14 for external memory interface or peripheral communication |+| 77 | D15 | tri_state | Data bus bit 15 for external memory interface or peripheral communication |+| 78 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 79 | EMU0 | input | Emulation pin 0 for on-chip debug and test access interface |+| 80 | EMU1/OFF | input | Emulation pin 1 or device power-down control signal for low-power standby mode |+| 81 | TDO | output | JTAG test data output from boundary scan logic at specified test clock frequency |+| 82 | TDI | input | JTAG test data input for boundary scan test instruction sequences |+| 83 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 84 | TRST | input | JTAG test reset input (active low) for resetting test access port state machine |+| 85 | TCK | input | JTAG test clock input for boundary scan operation requiring <100 MHz clock frequency |+| 86 | TMS | input | JTAG test mode select input for controlling test access port instruction sequences |+| 87 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 88 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 89 | SDA | bidirectional | I2C serial data open-drain line with internal pullup disabled by default |+| 90 | SCL | bidirectional | I2C serial clock open-drain line with internal pullup disabled by default |+| 91 | RESET | input | External reset input (active low) that initializes device and clears all registers when asserted |+| 92 | USBPLLVSS | power_in | USB PLL ground reference for phase-locked loop precision |+| 93 | INT0 | input | External interrupt input 0 for event-driven CPU interrupt generation |+| 94 | INT1 | input | External interrupt input 1 for event-driven CPU interrupt generation |+| 95 | USBPLLVDD | power_in | USB PLL supply voltage for phase-locked loop precision oscillator |+| 96 | INT2 | input | External interrupt input 2 for event-driven CPU interrupt generation |+| 97 | INT3 | input | External interrupt input 3 for event-driven CPU interrupt generation |+| 98 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 99 | INT4 | input | External interrupt input 4 for event-driven CPU interrupt generation |+| 100 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 101 | XF | output | External flag output signal controlled by CPU for peripheral signaling |+| 102 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 103 | ADVSS | power_in | Analog-to-digital converter digital ground reference for conversion accuracy |+| 104 | ADVDD | power_in | Analog-to-digital converter digital supply voltage 1.8V ±10% for successive approximation conversion |+| 105 | AIN0 | input | ADC analog input channel 0 for 10-bit successive approximation conversion |+| 106 | AIN1 | input | ADC analog input channel 1 for 10-bit successive approximation conversion |+| 107 | AVDD | power_in | ADC analog supply voltage 1.8V ±10% for analog-to-digital converter operation |+| 108 | AVSS | power_in | ADC analog ground reference for analog-to-digital converter precision |+| 109 | RDVDD | power_in | Real-time clock digital I/O supply voltage for oscillator interface |+| 110 | RCVDD | power_in | Real-time clock core supply voltage for independent oscillator operation |+| 111 | RTCINX2 | input | Real-time clock oscillator crystal input pin 2 for parallel resonant crystal operation |+| 112 | RTCINX1 | input | Real-time clock oscillator crystal input pin 1 for parallel resonant crystal operation |+| 113 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 114 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 115 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 116 | S23 | input | Serial port multiplexed signal 23 for McBSP port communication function |+| 117 | S25 | input | Serial port multiplexed signal 25 for McBSP port communication function |+| 118 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 119 | S24 | input | Serial port multiplexed signal 24 for McBSP port communication function |+| 120 | S21 | input | Serial port multiplexed signal 21 for McBSP port communication function |+| 121 | S22 | input | Serial port multiplexed signal 22 for McBSP port communication function |+| 122 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 123 | S20 | input | Serial port multiplexed signal 20 for McBSP port communication function |+| 124 | S13 | input | Serial port multiplexed signal 13 for McBSP port communication function |+| 125 | S15 | input | Serial port multiplexed signal 15 for McBSP port communication function |+| 126 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 127 | S14 | input | Serial port multiplexed signal 14 for McBSP port communication function |+| 128 | S11 | input | Serial port multiplexed signal 11 for McBSP port communication function |+| 129 | S12 | input | Serial port multiplexed signal 12 for McBSP port communication function |+| 130 | S10 | input | Serial port multiplexed signal 10 for McBSP port communication function |+| 131 | DX0 | output | McBSP0 data transmit output for serial port data communication |+| 132 | CVDD | power_in | Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant |+| 133 | FSX0 | output | McBSP0 transmit frame sync output for serial port frame synchronization |+| 134 | CLKX0 | output | McBSP0 transmit clock output for serial port timing |+| 135 | DR0 | input | McBSP0 data receive input for serial port data communication |+| 136 | FSR0 | input | McBSP0 receive frame sync input for serial port frame synchronization |+| 137 | CLKR0 | input | McBSP0 receive clock input for serial port timing |+| 138 | VSS | power_in | Ground reference pin for both core and I/O circuits |+| 139 | DVDD | power_in | Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins |+| 140 | TIN/TOUT0 | bidirectional | Timer 0 input/output pin configurable as input or output via TCR register |+| 141 | GPIO6 | input | General-purpose I/O pin 6, configurable as input or output via IODIR register |+| 142 | GPIO4 | input | General-purpose I/O pin 4, configurable as input or output via IODIR register |+| 143 | GPIO3 | input | General-purpose I/O pin 3, configurable as input or output via IODIR register |+| 144 | VSS | power_in | Ground reference pin for both core and I/O circuits |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-144(20x20) |+| Category | Embedded Processors & Controllers |+| Pins | 144 |++## CAD (KiCad official)++- Symbol: `TMS320VC5509APGE`+- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`+- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)+- 3D model files: `tms320vc5509apge-etched.step` / `tms320vc5509apge-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320vc5509apge.step` / `tms320vc5509apge.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320vc5509a) (150 pp, sha256 `ca806e8990aa030d`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320vc5509apge-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320vc5509apge",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320vc5509apge.kicad_sym",+ "tms320vc5509apge.kicad_mod",+ "tms320vc5509apge.glb",+ "tms320vc5509apge.step",+ "tms320vc5509apge.lbr",+ "docs/hero.png",+ "docs/tms320vc5509apge-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TMS320VC5509APGE",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-144(20x20)",+ "pin_count": 144,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320vc5509a",+ "parts": {+ "symbol": "tms320vc5509apge.kicad_sym",+ "footprint": "tms320vc5509apge.kicad_mod",+ "model_3d": "tms320vc5509apge-etched.glb",+ "model_3d_plain": "tms320vc5509apge.glb",+ "model_3d_step": "tms320vc5509apge-etched.step",+ "model_3d_step_plain": "tms320vc5509apge.step",+ "lbr": "tms320vc5509apge.lbr"+ },+ "distributor_links": {+ "lcsc": "C27653",+ "digikey": "296-17351-ND",+ "mouser": "595-MS320VC5509APGE"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T07:54:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-17351-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-MS320VC5509APGE",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "2",+ "name": "PU",+ "type": "output",+ "description": "USB internal pullup enable signal driven by device"+ },+ {+ "number": "3",+ "name": "DP",+ "type": "input",+ "description": "USB D+ differential signal input to transceiver with series resistor protection"+ },+ {+ "number": "4",+ "name": "DN",+ "type": "input",+ "description": "USB D- differential signal input to transceiver with series resistor protection"+ },+ {+ "number": "5",+ "name": "USBVDD",+ "type": "power_in",+ "description": "USB module I/O supply voltage 3.0V-3.6V for DP, DN, and PU pins"+ },+ {+ "number": "6",+ "name": "GPIO7",+ "type": "input",+ "description": "General-purpose I/O pin 7, configurable as input or output via IODIR register"+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "8",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "9",+ "name": "GPIO2",+ "type": "input",+ "description": "General-purpose I/O pin 2, configurable as input or output via IODIR register"+ },+ {+ "number": "10",+ "name": "GPIO1",+ "type": "input",+ "description": "General-purpose I/O pin 1, configurable as input or output via IODIR register"+ },+ {+ "number": "11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "12",+ "name": "GPIO0",+ "type": "input",+ "description": "General-purpose I/O pin 0 and mode select pin that determines parallel bus function configuration"+ },+ {+ "number": "13",+ "name": "X2/CLKIN",+ "type": "input",+ "description": "External clock input or crystal oscillator pin 2 accepting clock frequencies 6-20 MHz"+ },+ {+ "number": "14",+ "name": "X1",+ "type": "input",+ "description": "Crystal oscillator pin 1 for parallel resonant crystal connection"+ },+ {+ "number": "15",+ "name": "CLKOUT",+ "type": "output",+ "description": "Clock output from internal DPLL providing system clock or divided reference clock to external circuits"+ },+ {+ "number": "16",+ "name": "C0",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "17",+ "name": "C1",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "18",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "19",+ "name": "C2",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "20",+ "name": "C3",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "21",+ "name": "C4",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "22",+ "name": "C5",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "23",+ "name": "C6",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "24",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "25",+ "name": "C7",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "26",+ "name": "C8",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "27",+ "name": "C9",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "28",+ "name": "C11",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "29",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "30",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "31",+ "name": "C14",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "32",+ "name": "C12",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "33",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "34",+ "name": "C10",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "35",+ "name": "C13",+ "type": "tri_state",+ "description": "EMIF chip select or multiplexed signal functioning as external memory interface output"+ },+ {+ "number": "36",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "37",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "38",+ "name": "A13",+ "type": "tri_state",+ "description": "Address bus bit 13 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "39",+ "name": "A12",+ "type": "tri_state",+ "description": "Address bus bit 12 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "40",+ "name": "A11",+ "type": "tri_state",+ "description": "Address bus bit 11 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "41",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "42",+ "name": "A10",+ "type": "tri_state",+ "description": "Address bus bit 10 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "43",+ "name": "A9",+ "type": "tri_state",+ "description": "Address bus bit 9 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "44",+ "name": "A8",+ "type": "tri_state",+ "description": "Address bus bit 8 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "45",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "46",+ "name": "A7",+ "type": "tri_state",+ "description": "Address bus bit 7 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "47",+ "name": "A6",+ "type": "tri_state",+ "description": "Address bus bit 6 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "48",+ "name": "A5",+ "type": "tri_state",+ "description": "Address bus bit 5 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "49",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "50",+ "name": "A4",+ "type": "tri_state",+ "description": "Address bus bit 4 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "51",+ "name": "A3",+ "type": "tri_state",+ "description": "Address bus bit 3 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "52",+ "name": "A2",+ "type": "tri_state",+ "description": "Address bus bit 2 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "53",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "54",+ "name": "A1",+ "type": "tri_state",+ "description": "Address bus bit 1 for external memory interface or general-purpose I/O depending on EBSR setting"+ },+ {+ "number": "55",+ "name": "A0",+ "type": "tri_state",+ "description": "Address bus bit 0 for external memory interface or general-purpose I/O, XORed with A14 on EMIF"+ },+ {+ "number": "56",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "57",+ "name": "D0",+ "type": "tri_state",+ "description": "Data bus bit 0 for external memory interface or peripheral communication"+ },+ {+ "number": "58",+ "name": "D1",+ "type": "tri_state",+ "description": "Data bus bit 1 for external memory interface or peripheral communication"+ },+ {+ "number": "59",+ "name": "D2",+ "type": "tri_state",+ "description": "Data bus bit 2 for external memory interface or peripheral communication"+ },+ {+ "number": "60",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "61",+ "name": "D3",+ "type": "tri_state",+ "description": "Data bus bit 3 for external memory interface or peripheral communication"+ },+ {+ "number": "62",+ "name": "D4",+ "type": "tri_state",+ "description": "Data bus bit 4 for external memory interface or peripheral communication"+ },+ {+ "number": "63",+ "name": "D5",+ "type": "tri_state",+ "description": "Data bus bit 5 for external memory interface or peripheral communication"+ },+ {+ "number": "64",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "65",+ "name": "D6",+ "type": "tri_state",+ "description": "Data bus bit 6 for external memory interface or peripheral communication"+ },+ {+ "number": "66",+ "name": "D7",+ "type": "tri_state",+ "description": "Data bus bit 7 for external memory interface or peripheral communication"+ },+ {+ "number": "67",+ "name": "D8",+ "type": "tri_state",+ "description": "Data bus bit 8 for external memory interface or peripheral communication"+ },+ {+ "number": "68",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "69",+ "name": "D9",+ "type": "tri_state",+ "description": "Data bus bit 9 for external memory interface or peripheral communication"+ },+ {+ "number": "70",+ "name": "D10",+ "type": "tri_state",+ "description": "Data bus bit 10 for external memory interface or peripheral communication"+ },+ {+ "number": "71",+ "name": "D11",+ "type": "tri_state",+ "description": "Data bus bit 11 for external memory interface or peripheral communication"+ },+ {+ "number": "72",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "73",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "74",+ "name": "D12",+ "type": "tri_state",+ "description": "Data bus bit 12 for external memory interface or peripheral communication"+ },+ {+ "number": "75",+ "name": "D13",+ "type": "tri_state",+ "description": "Data bus bit 13 for external memory interface or peripheral communication"+ },+ {+ "number": "76",+ "name": "D14",+ "type": "tri_state",+ "description": "Data bus bit 14 for external memory interface or peripheral communication"+ },+ {+ "number": "77",+ "name": "D15",+ "type": "tri_state",+ "description": "Data bus bit 15 for external memory interface or peripheral communication"+ },+ {+ "number": "78",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "79",+ "name": "EMU0",+ "type": "input",+ "description": "Emulation pin 0 for on-chip debug and test access interface"+ },+ {+ "number": "80",+ "name": "EMU1/OFF",+ "type": "input",+ "description": "Emulation pin 1 or device power-down control signal for low-power standby mode"+ },+ {+ "number": "81",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output from boundary scan logic at specified test clock frequency"+ },+ {+ "number": "82",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input for boundary scan test instruction sequences"+ },+ {+ "number": "83",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "84",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset input (active low) for resetting test access port state machine"+ },+ {+ "number": "85",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input for boundary scan operation requiring <100 MHz clock frequency"+ },+ {+ "number": "86",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input for controlling test access port instruction sequences"+ },+ {+ "number": "87",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "88",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "89",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C serial data open-drain line with internal pullup disabled by default"+ },+ {+ "number": "90",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C serial clock open-drain line with internal pullup disabled by default"+ },+ {+ "number": "91",+ "name": "RESET",+ "type": "input",+ "description": "External reset input (active low) that initializes device and clears all registers when asserted"+ },+ {+ "number": "92",+ "name": "USBPLLVSS",+ "type": "power_in",+ "description": "USB PLL ground reference for phase-locked loop precision"+ },+ {+ "number": "93",+ "name": "INT0",+ "type": "input",+ "description": "External interrupt input 0 for event-driven CPU interrupt generation"+ },+ {+ "number": "94",+ "name": "INT1",+ "type": "input",+ "description": "External interrupt input 1 for event-driven CPU interrupt generation"+ },+ {+ "number": "95",+ "name": "USBPLLVDD",+ "type": "power_in",+ "description": "USB PLL supply voltage for phase-locked loop precision oscillator"+ },+ {+ "number": "96",+ "name": "INT2",+ "type": "input",+ "description": "External interrupt input 2 for event-driven CPU interrupt generation"+ },+ {+ "number": "97",+ "name": "INT3",+ "type": "input",+ "description": "External interrupt input 3 for event-driven CPU interrupt generation"+ },+ {+ "number": "98",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "99",+ "name": "INT4",+ "type": "input",+ "description": "External interrupt input 4 for event-driven CPU interrupt generation"+ },+ {+ "number": "100",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "101",+ "name": "XF",+ "type": "output",+ "description": "External flag output signal controlled by CPU for peripheral signaling"+ },+ {+ "number": "102",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "103",+ "name": "ADVSS",+ "type": "power_in",+ "description": "Analog-to-digital converter digital ground reference for conversion accuracy"+ },+ {+ "number": "104",+ "name": "ADVDD",+ "type": "power_in",+ "description": "Analog-to-digital converter digital supply voltage 1.8V ±10% for successive approximation conversion"+ },+ {+ "number": "105",+ "name": "AIN0",+ "type": "input",+ "description": "ADC analog input channel 0 for 10-bit successive approximation conversion"+ },+ {+ "number": "106",+ "name": "AIN1",+ "type": "input",+ "description": "ADC analog input channel 1 for 10-bit successive approximation conversion"+ },+ {+ "number": "107",+ "name": "AVDD",+ "type": "power_in",+ "description": "ADC analog supply voltage 1.8V ±10% for analog-to-digital converter operation"+ },+ {+ "number": "108",+ "name": "AVSS",+ "type": "power_in",+ "description": "ADC analog ground reference for analog-to-digital converter precision"+ },+ {+ "number": "109",+ "name": "RDVDD",+ "type": "power_in",+ "description": "Real-time clock digital I/O supply voltage for oscillator interface"+ },+ {+ "number": "110",+ "name": "RCVDD",+ "type": "power_in",+ "description": "Real-time clock core supply voltage for independent oscillator operation"+ },+ {+ "number": "111",+ "name": "RTCINX2",+ "type": "input",+ "description": "Real-time clock oscillator crystal input pin 2 for parallel resonant crystal operation"+ },+ {+ "number": "112",+ "name": "RTCINX1",+ "type": "input",+ "description": "Real-time clock oscillator crystal input pin 1 for parallel resonant crystal operation"+ },+ {+ "number": "113",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "114",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "115",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "116",+ "name": "S23",+ "type": "input",+ "description": "Serial port multiplexed signal 23 for McBSP port communication function"+ },+ {+ "number": "117",+ "name": "S25",+ "type": "input",+ "description": "Serial port multiplexed signal 25 for McBSP port communication function"+ },+ {+ "number": "118",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "119",+ "name": "S24",+ "type": "input",+ "description": "Serial port multiplexed signal 24 for McBSP port communication function"+ },+ {+ "number": "120",+ "name": "S21",+ "type": "input",+ "description": "Serial port multiplexed signal 21 for McBSP port communication function"+ },+ {+ "number": "121",+ "name": "S22",+ "type": "input",+ "description": "Serial port multiplexed signal 22 for McBSP port communication function"+ },+ {+ "number": "122",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "123",+ "name": "S20",+ "type": "input",+ "description": "Serial port multiplexed signal 20 for McBSP port communication function"+ },+ {+ "number": "124",+ "name": "S13",+ "type": "input",+ "description": "Serial port multiplexed signal 13 for McBSP port communication function"+ },+ {+ "number": "125",+ "name": "S15",+ "type": "input",+ "description": "Serial port multiplexed signal 15 for McBSP port communication function"+ },+ {+ "number": "126",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "127",+ "name": "S14",+ "type": "input",+ "description": "Serial port multiplexed signal 14 for McBSP port communication function"+ },+ {+ "number": "128",+ "name": "S11",+ "type": "input",+ "description": "Serial port multiplexed signal 11 for McBSP port communication function"+ },+ {+ "number": "129",+ "name": "S12",+ "type": "input",+ "description": "Serial port multiplexed signal 12 for McBSP port communication function"+ },+ {+ "number": "130",+ "name": "S10",+ "type": "input",+ "description": "Serial port multiplexed signal 10 for McBSP port communication function"+ },+ {+ "number": "131",+ "name": "DX0",+ "type": "output",+ "description": "McBSP0 data transmit output for serial port data communication"+ },+ {+ "number": "132",+ "name": "CVDD",+ "type": "power_in",+ "description": "Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant"+ },+ {+ "number": "133",+ "name": "FSX0",+ "type": "output",+ "description": "McBSP0 transmit frame sync output for serial port frame synchronization"+ },+ {+ "number": "134",+ "name": "CLKX0",+ "type": "output",+ "description": "McBSP0 transmit clock output for serial port timing"+ },+ {+ "number": "135",+ "name": "DR0",+ "type": "input",+ "description": "McBSP0 data receive input for serial port data communication"+ },+ {+ "number": "136",+ "name": "FSR0",+ "type": "input",+ "description": "McBSP0 receive frame sync input for serial port frame synchronization"+ },+ {+ "number": "137",+ "name": "CLKR0",+ "type": "input",+ "description": "McBSP0 receive clock input for serial port timing"+ },+ {+ "number": "138",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ },+ {+ "number": "139",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins"+ },+ {+ "number": "140",+ "name": "TIN/TOUT0",+ "type": "bidirectional",+ "description": "Timer 0 input/output pin configurable as input or output via TCR register"+ },+ {+ "number": "141",+ "name": "GPIO6",+ "type": "input",+ "description": "General-purpose I/O pin 6, configurable as input or output via IODIR register"+ },+ {+ "number": "142",+ "name": "GPIO4",+ "type": "input",+ "description": "General-purpose I/O pin 4, configurable as input or output via IODIR register"+ },+ {+ "number": "143",+ "name": "GPIO3",+ "type": "input",+ "description": "General-purpose I/O pin 3, configurable as input or output via IODIR register"+ },+ {+ "number": "144",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference pin for both core and I/O circuits"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Serial port multiplexed signals S10-S25 lack detailed functional descriptions in the provided datash; SDA and SCL pins are I2C open-drain lines; datasheet text on PAGE 67 notes 'I2C protocol compatible,; Address bus A[0:13] behavior is mode-dependent per GPIO0 and External Bus Selection Register; functi"+ ],+ "pages_sent": 26,+ "cost_usd": 0.4112,+ "at": "2026-10-01T07:54:01"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320vc5509a",+ "pages": 150,+ "sha256": "ca806e8990aa030d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 144,+ "described": 144,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}