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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS320VC5509APGE

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

TMS320VC5509APGE from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSS	power_in	Ground reference pin for both core and I/O circuits
2	PU	output	USB internal pullup enable signal driven by device
3	DP	input	USB D+ differential signal input to transceiver with series resistor protection
4	DN	input	USB D- differential signal input to transceiver with series resistor protection
5	USBVDD	power_in	USB module I/O supply voltage 3.0V-3.6V for DP, DN, and PU pins
6	GPIO7	input	General-purpose I/O pin 7, configurable as input or output via IODIR register
7	VSS	power_in	Ground reference pin for both core and I/O circuits
8	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
9	GPIO2	input	General-purpose I/O pin 2, configurable as input or output via IODIR register
10	GPIO1	input	General-purpose I/O pin 1, configurable as input or output via IODIR register
11	VSS	power_in	Ground reference pin for both core and I/O circuits
12	GPIO0	input	General-purpose I/O pin 0 and mode select pin that determines parallel bus function configuration
13	X2/CLKIN	input	External clock input or crystal oscillator pin 2 accepting clock frequencies 6-20 MHz
14	X1	input	Crystal oscillator pin 1 for parallel resonant crystal connection
15	CLKOUT	output	Clock output from internal DPLL providing system clock or divided reference clock to external circuits
16	C0	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
17	C1	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
18	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
19	C2	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
20	C3	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
21	C4	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
22	C5	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
23	C6	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
24	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
25	C7	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
26	C8	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
27	C9	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
28	C11	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
29	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
30	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
31	C14	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
32	C12	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
33	VSS	power_in	Ground reference pin for both core and I/O circuits
34	C10	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
35	C13	tri_state	EMIF chip select or multiplexed signal functioning as external memory interface output
36	VSS	power_in	Ground reference pin for both core and I/O circuits
37	VSS	power_in	Ground reference pin for both core and I/O circuits
38	A13	tri_state	Address bus bit 13 for external memory interface or general-purpose I/O depending on EBSR setting
39	A12	tri_state	Address bus bit 12 for external memory interface or general-purpose I/O depending on EBSR setting
40	A11	tri_state	Address bus bit 11 for external memory interface or general-purpose I/O depending on EBSR setting
41	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
42	A10	tri_state	Address bus bit 10 for external memory interface or general-purpose I/O depending on EBSR setting
43	A9	tri_state	Address bus bit 9 for external memory interface or general-purpose I/O depending on EBSR setting
44	A8	tri_state	Address bus bit 8 for external memory interface or general-purpose I/O depending on EBSR setting
45	VSS	power_in	Ground reference pin for both core and I/O circuits
46	A7	tri_state	Address bus bit 7 for external memory interface or general-purpose I/O depending on EBSR setting
47	A6	tri_state	Address bus bit 6 for external memory interface or general-purpose I/O depending on EBSR setting
48	A5	tri_state	Address bus bit 5 for external memory interface or general-purpose I/O depending on EBSR setting
49	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
50	A4	tri_state	Address bus bit 4 for external memory interface or general-purpose I/O depending on EBSR setting
51	A3	tri_state	Address bus bit 3 for external memory interface or general-purpose I/O depending on EBSR setting
52	A2	tri_state	Address bus bit 2 for external memory interface or general-purpose I/O depending on EBSR setting
53	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
54	A1	tri_state	Address bus bit 1 for external memory interface or general-purpose I/O depending on EBSR setting
55	A0	tri_state	Address bus bit 0 for external memory interface or general-purpose I/O, XORed with A14 on EMIF
56	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
57	D0	tri_state	Data bus bit 0 for external memory interface or peripheral communication
58	D1	tri_state	Data bus bit 1 for external memory interface or peripheral communication
59	D2	tri_state	Data bus bit 2 for external memory interface or peripheral communication
60	VSS	power_in	Ground reference pin for both core and I/O circuits
61	D3	tri_state	Data bus bit 3 for external memory interface or peripheral communication
62	D4	tri_state	Data bus bit 4 for external memory interface or peripheral communication
63	D5	tri_state	Data bus bit 5 for external memory interface or peripheral communication
64	VSS	power_in	Ground reference pin for both core and I/O circuits
65	D6	tri_state	Data bus bit 6 for external memory interface or peripheral communication
66	D7	tri_state	Data bus bit 7 for external memory interface or peripheral communication
67	D8	tri_state	Data bus bit 8 for external memory interface or peripheral communication
68	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
69	D9	tri_state	Data bus bit 9 for external memory interface or peripheral communication
70	D10	tri_state	Data bus bit 10 for external memory interface or peripheral communication
71	D11	tri_state	Data bus bit 11 for external memory interface or peripheral communication
72	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
73	VSS	power_in	Ground reference pin for both core and I/O circuits
74	D12	tri_state	Data bus bit 12 for external memory interface or peripheral communication
75	D13	tri_state	Data bus bit 13 for external memory interface or peripheral communication
76	D14	tri_state	Data bus bit 14 for external memory interface or peripheral communication
77	D15	tri_state	Data bus bit 15 for external memory interface or peripheral communication
78	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
79	EMU0	input	Emulation pin 0 for on-chip debug and test access interface
80	EMU1/OFF	input	Emulation pin 1 or device power-down control signal for low-power standby mode
81	TDO	output	JTAG test data output from boundary scan logic at specified test clock frequency
82	TDI	input	JTAG test data input for boundary scan test instruction sequences
83	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
84	TRST	input	JTAG test reset input (active low) for resetting test access port state machine
85	TCK	input	JTAG test clock input for boundary scan operation requiring <100 MHz clock frequency
86	TMS	input	JTAG test mode select input for controlling test access port instruction sequences
87	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
88	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
89	SDA	bidirectional	I2C serial data open-drain line with internal pullup disabled by default
90	SCL	bidirectional	I2C serial clock open-drain line with internal pullup disabled by default
91	RESET	input	External reset input (active low) that initializes device and clears all registers when asserted
92	USBPLLVSS	power_in	USB PLL ground reference for phase-locked loop precision
93	INT0	input	External interrupt input 0 for event-driven CPU interrupt generation
94	INT1	input	External interrupt input 1 for event-driven CPU interrupt generation
95	USBPLLVDD	power_in	USB PLL supply voltage for phase-locked loop precision oscillator
96	INT2	input	External interrupt input 2 for event-driven CPU interrupt generation
97	INT3	input	External interrupt input 3 for event-driven CPU interrupt generation
98	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
99	INT4	input	External interrupt input 4 for event-driven CPU interrupt generation
100	VSS	power_in	Ground reference pin for both core and I/O circuits
101	XF	output	External flag output signal controlled by CPU for peripheral signaling
102	VSS	power_in	Ground reference pin for both core and I/O circuits
103	ADVSS	power_in	Analog-to-digital converter digital ground reference for conversion accuracy
104	ADVDD	power_in	Analog-to-digital converter digital supply voltage 1.8V ±10% for successive approximation conversion
105	AIN0	input	ADC analog input channel 0 for 10-bit successive approximation conversion
106	AIN1	input	ADC analog input channel 1 for 10-bit successive approximation conversion
107	AVDD	power_in	ADC analog supply voltage 1.8V ±10% for analog-to-digital converter operation
108	AVSS	power_in	ADC analog ground reference for analog-to-digital converter precision
109	RDVDD	power_in	Real-time clock digital I/O supply voltage for oscillator interface
110	RCVDD	power_in	Real-time clock core supply voltage for independent oscillator operation
111	RTCINX2	input	Real-time clock oscillator crystal input pin 2 for parallel resonant crystal operation
112	RTCINX1	input	Real-time clock oscillator crystal input pin 1 for parallel resonant crystal operation
113	VSS	power_in	Ground reference pin for both core and I/O circuits
114	VSS	power_in	Ground reference pin for both core and I/O circuits
115	VSS	power_in	Ground reference pin for both core and I/O circuits
116	S23	input	Serial port multiplexed signal 23 for McBSP port communication function
117	S25	input	Serial port multiplexed signal 25 for McBSP port communication function
118	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
119	S24	input	Serial port multiplexed signal 24 for McBSP port communication function
120	S21	input	Serial port multiplexed signal 21 for McBSP port communication function
121	S22	input	Serial port multiplexed signal 22 for McBSP port communication function
122	VSS	power_in	Ground reference pin for both core and I/O circuits
123	S20	input	Serial port multiplexed signal 20 for McBSP port communication function
124	S13	input	Serial port multiplexed signal 13 for McBSP port communication function
125	S15	input	Serial port multiplexed signal 15 for McBSP port communication function
126	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
127	S14	input	Serial port multiplexed signal 14 for McBSP port communication function
128	S11	input	Serial port multiplexed signal 11 for McBSP port communication function
129	S12	input	Serial port multiplexed signal 12 for McBSP port communication function
130	S10	input	Serial port multiplexed signal 10 for McBSP port communication function
131	DX0	output	McBSP0 data transmit output for serial port data communication
132	CVDD	power_in	Core supply voltage 1.2V, 1.35V, or 1.6V depending on frequency variant
133	FSX0	output	McBSP0 transmit frame sync output for serial port frame synchronization
134	CLKX0	output	McBSP0 transmit clock output for serial port timing
135	DR0	input	McBSP0 data receive input for serial port data communication
136	FSR0	input	McBSP0 receive frame sync input for serial port frame synchronization
137	CLKR0	input	McBSP0 receive clock input for serial port timing
138	VSS	power_in	Ground reference pin for both core and I/O circuits
139	DVDD	power_in	Digital I/O power supply voltage 2.7V-3.6V for I/O interface pins
140	TIN/TOUT0	bidirectional	Timer 0 input/output pin configurable as input or output via TCR register
141	GPIO6	input	General-purpose I/O pin 6, configurable as input or output via IODIR register
142	GPIO4	input	General-purpose I/O pin 4, configurable as input or output via IODIR register
143	GPIO3	input	General-purpose I/O pin 3, configurable as input or output via IODIR register
144	VSS	power_in	Ground reference pin for both core and I/O circuits

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-144(20x20)
Category	Embedded Processors & Controllers
Pins	144

CAD (KiCad official)

Symbol: TMS320VC5509APGE
Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
3D model files: tms320vc5509apge-etched.step / tms320vc5509apge-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320vc5509apge.step / tms320vc5509apge.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (150 pp, sha256 ca806e8990aa030d, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF