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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS320VC5506PGE

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-144(20x20)

TMS320VC5506PGE from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSS	power_in	Ground for both the I/O pins and the core.
2	PU	output	USB pull-up pin; VOH is at least 0.9 × USBVDD at IOH = −300 µA with USBVDD = 3.0 V to 3.6 V.
3	DP	bidirectional	USB full-speed D+ data pin; it tolerates a short to 0 V or 5 V only when the recommended series resistors are connected.
4	DN	bidirectional	USB full-speed D− data pin; it tolerates a short to 0 V or 5 V only when the recommended series resistors are connected.
5	USBVDD	power_in	USB module I/O supply for DP, DN and PU, specified at 3.0 V to 3.6 V.
6	GPIO7	bidirectional	One of the seven dedicated general-purpose I/O pins on the LQFP package.
7	VSS	power_in	Ground for both the I/O pins and the core.
8	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
9	GPIO2	bidirectional	One of the seven dedicated general-purpose I/O pins on the LQFP package.
10	GPIO1	bidirectional	One of the seven dedicated general-purpose I/O pins on the LQFP package.
11	VSS	power_in	Ground for both the I/O pins and the core.
12	GPIO0	bidirectional	Dedicated general-purpose I/O pin that also sets the initial state of the address pins A[13:0].
13	X2/CLKIN	input	Crystal connection or external clock input; when an external clock is used, X1 is left unconnected.
14	X1	passive	Crystal connection for the internal oscillator; left unconnected when an external clock drives X2/CLKIN.
15	CLKOUT	output	Clock output; its function and switching limits are not stated in the provided pages.
16	C0	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
17	C1	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
18	CVDD	power_in	Core power supply; the core operates at 1.2 V.
19	C2	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
20	C3	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
21	C4	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
22	C5	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
23	C6	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
24	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
25	C7	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
26	C8	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
27	C9	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
28	C11	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
29	CVDD	power_in	Core power supply; the core operates at 1.2 V.
30	CVDD	power_in	Core power supply; the core operates at 1.2 V.
31	C14	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
32	C12	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
33	VSS	power_in	Ground for both the I/O pins and the core.
34	C10	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
35	C13	bidirectional	Function and electrical limits are not stated in the provided pages; pin assignment per Table 2-2.
36	VSS	power_in	Ground for both the I/O pins and the core.
37	VSS	power_in	Ground for both the I/O pins and the core.
38	A13	bidirectional	Parallel address bus bit, serving as EMIF.A13 or GPIO.A13 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
39	A12	bidirectional	Parallel address bus bit, serving as EMIF.A12 or GPIO.A12 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
40	A11	bidirectional	Parallel address bus bit, serving as EMIF.A11 or GPIO.A11 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
41	CVDD	power_in	Core power supply; the core operates at 1.2 V.
42	A10	bidirectional	Parallel address bus bit, serving as EMIF.A10 or GPIO.A10 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
43	A9	bidirectional	Parallel address bus bit, serving as EMIF.A9 or GPIO.A9 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
44	A8	bidirectional	Parallel address bus bit, serving as EMIF.A8 or GPIO.A8 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
45	VSS	power_in	Ground for both the I/O pins and the core.
46	A7	bidirectional	Parallel address bus bit, serving as EMIF.A7 or GPIO.A7 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
47	A6	bidirectional	Parallel address bus bit, serving as EMIF.A6 or GPIO.A6 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
48	A5	bidirectional	Parallel address bus bit, serving as EMIF.A5 or GPIO.A5 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
49	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
50	A4	bidirectional	Parallel address bus bit, serving as EMIF.A4 or GPIO.A4 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
51	A3	bidirectional	Parallel address bus bit, serving as EMIF.A3 or GPIO.A3 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
52	A2	bidirectional	Parallel address bus bit, serving as EMIF.A2 or GPIO.A2 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
53	CVDD	power_in	Core power supply; the core operates at 1.2 V.
54	A1	bidirectional	Parallel address bus bit, serving as EMIF.A1 or GPIO.A1 depending on the Parallel Port Mode field; it has a bus holder that keeps its level in high-impedance state.
55	A0	bidirectional	Parallel address bus bit; on EMIF mode it carries A0 XORed with internal A14, or serves as GPIO.A0 depending on the Parallel Port Mode field.
56	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
57	D0	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
58	D1	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
59	D2	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
60	VSS	power_in	Ground for both the I/O pins and the core.
61	D3	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
62	D4	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
63	D5	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
64	VSS	power_in	Ground for both the I/O pins and the core.
65	D6	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
66	D7	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
67	D8	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
68	CVDD	power_in	Core power supply; the core operates at 1.2 V.
69	D9	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
70	D10	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
71	D11	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
72	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
73	VSS	power_in	Ground for both the I/O pins and the core.
74	D12	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
75	D13	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
76	D14	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
77	D15	bidirectional	Data bus bit; function and electrical limits are not stated in the provided pages.
78	CVDD	power_in	Core power supply; the core operates at 1.2 V.
79	EMU0	bidirectional	Emulation pin; function and electrical limits are not stated in the provided pages.
80	EMU1/OFF	bidirectional	Emulation pin (EMU1) that also selects the OFF function; function and limits are not stated in the provided pages.
81	TDO	tri_state	JTAG test data output; function and electrical limits are not stated in the provided pages.
82	TDI	input	JTAG test data input; function and electrical limits are not stated in the provided pages.
83	CVDD	power_in	Core power supply; the core operates at 1.2 V.
84	TRST	input	JTAG test reset input; function and electrical limits are not stated in the provided pages.
85	TCK	input	JTAG test clock input; function and electrical limits are not stated in the provided pages.
86	TMS	input	JTAG test mode select input; function and electrical limits are not stated in the provided pages.
87	CVDD	power_in	Core power supply; the core operates at 1.2 V.
88	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
89	SDA	bidirectional	I2C data line; it has no fail-safe buffer and can draw current when the device is powered down.
90	SCL	bidirectional	I2C clock line; it has no fail-safe buffer and can draw current when the device is powered down.
91	RESET	input	Device reset input; reset timing limits are not stated in the provided pages.
92	USBPLLVSS	power_in	Dedicated ground for the USB PLL.
93	INT0	input	External interrupt input; function and timing limits are not stated in the provided pages.
94	INT1	input	External interrupt input; function and timing limits are not stated in the provided pages.
95	USBPLLVDD	power_in	Dedicated supply for the USB PLL.
96	INT2	input	External interrupt input; function and timing limits are not stated in the provided pages.
97	INT3	input	External interrupt input; function and timing limits are not stated in the provided pages.
98	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
99	INT4	input	External interrupt input; function and timing limits are not stated in the provided pages.
100	VSS	power_in	Ground for both the I/O pins and the core.
101	XF	output	General-purpose output pin (XF) of the device.
102	VSS	power_in	Ground for both the I/O pins and the core.
103	VSS	power_in	Ground for both the I/O pins and the core.
104	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
105	NC	unconnected	No connection, as listed in Table 2-2.
106	NC	unconnected	No connection, as listed in Table 2-2.
107	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
108	VSS	power_in	Ground for both the I/O pins and the core.
109	RDVDD	power_in	RTC module I/O supply.
110	RCVDD	power_in	RTC module core supply.
111	RTCINX2	passive	Real-time clock crystal connection; function and limits are not stated in the provided pages.
112	RTCINX1	passive	Real-time clock crystal connection; function and limits are not stated in the provided pages.
113	VSS	power_in	Ground for both the I/O pins and the core.
114	VSS	power_in	Ground for both the I/O pins and the core.
115	VSS	power_in	Ground for both the I/O pins and the core.
116	DX2	output	Multichannel serial port 2 transmit data; function and limits are not stated in the provided pages.
117	FSX2	bidirectional	Multichannel serial port 2 transmit frame sync; function and limits are not stated in the provided pages.
118	CVDD	power_in	Core power supply; the core operates at 1.2 V.
119	CLKX2	bidirectional	Multichannel serial port 2 transmit clock; function and limits are not stated in the provided pages.
120	DR2	input	Multichannel serial port 2 receive data; function and limits are not stated in the provided pages.
121	FSR2	bidirectional	Multichannel serial port 2 receive frame sync; function and limits are not stated in the provided pages.
122	VSS	power_in	Ground for both the I/O pins and the core.
123	CLKR2	bidirectional	Multichannel serial port 2 receive clock; function and limits are not stated in the provided pages.
124	DX1	output	Multichannel serial port 1 transmit data; function and limits are not stated in the provided pages.
125	FSX1	bidirectional	Multichannel serial port 1 transmit frame sync; function and limits are not stated in the provided pages.
126	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
127	CLKX1	bidirectional	Multichannel serial port 1 transmit clock; function and limits are not stated in the provided pages.
128	DR1	input	Multichannel serial port 1 receive data; function and limits are not stated in the provided pages.
129	FSR1	bidirectional	Multichannel serial port 1 receive frame sync; function and limits are not stated in the provided pages.
130	CLKR1	bidirectional	Multichannel serial port 1 receive clock; function and limits are not stated in the provided pages.
131	DX0	output	Multichannel serial port 0 transmit data; function and limits are not stated in the provided pages.
132	CVDD	power_in	Core power supply; the core operates at 1.2 V.
133	FSX0	bidirectional	Multichannel serial port 0 transmit frame sync; function and limits are not stated in the provided pages.
134	CLKX0	bidirectional	Multichannel serial port 0 transmit clock; function and limits are not stated in the provided pages.
135	DR0	input	Multichannel serial port 0 receive data; function and limits are not stated in the provided pages.
136	FSR0	bidirectional	Multichannel serial port 0 receive frame sync; function and limits are not stated in the provided pages.
137	CLKR0	bidirectional	Multichannel serial port 0 receive clock; function and limits are not stated in the provided pages.
138	VSS	power_in	Ground for both the I/O pins and the core.
139	DVDD	power_in	Power supply for the I/O pins; I/O range is 2.7 V to 3.6 V.
140	TIN/TOUT0	bidirectional	Timer0 input/output pin; function and timing limits are not stated in the provided pages.
141	GPIO6	bidirectional	One of the seven dedicated general-purpose I/O pins on the LQFP package.
142	GPIO4	bidirectional	One of the seven dedicated general-purpose I/O pins on the LQFP package.
143	GPIO3	bidirectional	One of the seven dedicated general-purpose I/O pins on the LQFP package.
144	VSS	power_in	Ground for both the I/O pins and the core.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-144(20x20)
Category	Embedded Processors & Controllers
Pins	144

CAD (KiCad official)

Symbol: TMS320VC5506PGE
Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
3D model files: tms320vc5506pge-etched.step / tms320vc5506pge-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320vc5506pge.step / tms320vc5506pge.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (122 pp, sha256 b1395919f8c4ca6b, retrieved 2026-10-12, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF