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TMS320VC33PGE150
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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+180@@ -0,0 +1,180 @@+# TMS320VC33PGE150++**Texas Instruments** · Digital Signal Processors (DSP/DSC) · LQFP-144(20x20)++TMS320VC33PGE150 from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A20 | tri_state | 24-bit primary-bus address output bit A20; high-impedance when SHZ, HOLD, or RESET is active. |+| 2 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 3 | A19 | tri_state | 24-bit primary-bus address output bit A19; high-impedance when SHZ, HOLD, or RESET is active. |+| 4 | A18 | tri_state | 24-bit primary-bus address output bit A18; high-impedance when SHZ, HOLD, or RESET is active. |+| 5 | A17 | tri_state | 24-bit primary-bus address output bit A17; high-impedance when SHZ, HOLD, or RESET is active. |+| 6 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 7 | A16 | tri_state | 24-bit primary-bus address output bit A16; high-impedance when SHZ, HOLD, or RESET is active. |+| 8 | A15 | tri_state | 24-bit primary-bus address output bit A15; high-impedance when SHZ, HOLD, or RESET is active. |+| 9 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 10 | A14 | tri_state | 24-bit primary-bus address output bit A14; high-impedance when SHZ, HOLD, or RESET is active. |+| 11 | A13 | tri_state | 24-bit primary-bus address output bit A13; high-impedance when SHZ, HOLD, or RESET is active. |+| 12 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 13 | A12 | tri_state | 24-bit primary-bus address output bit A12; high-impedance when SHZ, HOLD, or RESET is active. |+| 14 | A11 | tri_state | 24-bit primary-bus address output bit A11; high-impedance when SHZ, HOLD, or RESET is active. |+| 15 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 16 | A10 | tri_state | 24-bit primary-bus address output bit A10; high-impedance when SHZ, HOLD, or RESET is active. |+| 17 | A9 | tri_state | 24-bit primary-bus address output bit A9; high-impedance when SHZ, HOLD, or RESET is active. |+| 18 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 19 | A8 | tri_state | 24-bit primary-bus address output bit A8; high-impedance when SHZ, HOLD, or RESET is active. |+| 20 | A7 | tri_state | 24-bit primary-bus address output bit A7; high-impedance when SHZ, HOLD, or RESET is active. |+| 21 | A6 | tri_state | 24-bit primary-bus address output bit A6; high-impedance when SHZ, HOLD, or RESET is active. |+| 22 | A5 | tri_state | 24-bit primary-bus address output bit A5; high-impedance when SHZ, HOLD, or RESET is active. |+| 23 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 24 | A4 | tri_state | 24-bit primary-bus address output bit A4; high-impedance when SHZ, HOLD, or RESET is active. |+| 25 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 26 | A3 | tri_state | 24-bit primary-bus address output bit A3; high-impedance when SHZ, HOLD, or RESET is active. |+| 27 | A2 | tri_state | 24-bit primary-bus address output bit A2; high-impedance when SHZ, HOLD, or RESET is active. |+| 28 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 29 | A1 | tri_state | 24-bit primary-bus address output bit A1; high-impedance when SHZ, HOLD, or RESET is active. |+| 30 | A0 | tri_state | 24-bit primary-bus address output bit A0; high-impedance when SHZ, HOLD, or RESET is active. |+| 31 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 32 | PAGE3 | tri_state | Decoded page strobe 3 for external access; high-impedance when SHZ, HOLD, or RESET is active. |+| 33 | PAGE2 | tri_state | Decoded page strobe 2 for external access; high-impedance when SHZ, HOLD, or RESET is active. |+| 34 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 35 | PAGE1 | tri_state | Decoded page strobe 1 for external access; high-impedance when SHZ, HOLD, or RESET is active. |+| 36 | PAGE0 | tri_state | Decoded page strobe 0 for external access; high-impedance when SHZ, HOLD, or RESET is active. |+| 37 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 38 | H1 | tri_state | External H1 clock output; high-impedance when SHZ is active. |+| 39 | H3 | tri_state | External H3 clock output; high-impedance when SHZ is active. |+| 40 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 41 | STRB | tri_state | Strobe output for all external accesses; high-impedance when SHZ or HOLD is active. |+| 42 | R/W | tri_state | Read/write output: high for a read and low for a write over the parallel interface; high-impedance when SHZ, HOLD, or RESET is active. |+| 43 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 44 | IACK | tri_state | Interrupt acknowledge output generated by the IACK instruction, which can indicate when a section of code is executing; high-impedance when SHZ is active. |+| 45 | RDY | input | Ready input indicating that the external device is prepared for transaction completion. |+| 46 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 47 | HOLD | input | Hold input: when low, the ongoing transaction completes and the address, data, STRB and R/W outputs go high-impedance until HOLD returns high or the NOHOLD bit is set. |+| 48 | HOLDA | tri_state | Hold acknowledge output asserted in response to a logic-low on HOLD, indicating the primary bus is high-impedance and transactions are held; high-impedance when SHZ is active. |+| 49 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 50 | D31 | bidirectional | Primary-bus 32-bit data port bit D31 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 51 | D30 | bidirectional | Primary-bus 32-bit data port bit D30 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 52 | D29 | bidirectional | Primary-bus 32-bit data port bit D29 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 53 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 54 | D28 | bidirectional | Primary-bus 32-bit data port bit D28 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 55 | D27 | bidirectional | Primary-bus 32-bit data port bit D27 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 56 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 57 | D26 | bidirectional | Primary-bus 32-bit data port bit D26 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 58 | D25 | bidirectional | Primary-bus 32-bit data port bit D25 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 59 | D24 | bidirectional | Primary-bus 32-bit data port bit D24 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 60 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 61 | D23 | bidirectional | Primary-bus 32-bit data port bit D23 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 62 | D22 | bidirectional | Primary-bus 32-bit data port bit D22 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 63 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 64 | D21 | bidirectional | Primary-bus 32-bit data port bit D21 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 65 | D20 | bidirectional | Primary-bus 32-bit data port bit D20 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 66 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 67 | D19 | bidirectional | Primary-bus 32-bit data port bit D19 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 68 | D18 | bidirectional | Primary-bus 32-bit data port bit D18 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 69 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 70 | D17 | bidirectional | Primary-bus 32-bit data port bit D17 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 71 | D16 | bidirectional | Primary-bus 32-bit data port bit D16 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 72 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 73 | D15 | bidirectional | Primary-bus 32-bit data port bit D15 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 74 | D14 | bidirectional | Primary-bus 32-bit data port bit D14 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 75 | D13 | bidirectional | Primary-bus 32-bit data port bit D13 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 76 | D12 | bidirectional | Primary-bus 32-bit data port bit D12 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 77 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 78 | D11 | bidirectional | Primary-bus 32-bit data port bit D11 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 79 | D10 | bidirectional | Primary-bus 32-bit data port bit D10 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 80 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 81 | D9 | bidirectional | Primary-bus 32-bit data port bit D9 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 82 | D8 | bidirectional | Primary-bus 32-bit data port bit D8 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 83 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 84 | D7 | bidirectional | Primary-bus 32-bit data port bit D7 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 85 | D6 | bidirectional | Primary-bus 32-bit data port bit D6 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 86 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 87 | D5 | bidirectional | Primary-bus 32-bit data port bit D5 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 88 | D4 | bidirectional | Primary-bus 32-bit data port bit D4 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 89 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 90 | D3 | bidirectional | Primary-bus 32-bit data port bit D3 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 91 | D2 | bidirectional | Primary-bus 32-bit data port bit D2 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 92 | D1 | bidirectional | Primary-bus 32-bit data port bit D1 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 93 | D0 | bidirectional | Primary-bus 32-bit data port bit D0 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active. |+| 94 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 95 | EMU1 | bidirectional | JTAG emulation pin 1; use an individual pullup to DVDD. |+| 96 | EMU0 | bidirectional | JTAG emulation pin 0; use an individual pullup to DVDD. |+| 97 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 98 | TCK | input | JTAG test clock input; has an internal pullup. |+| 99 | TDO | output | JTAG test data output. |+| 100 | TDI | input | JTAG test data input; has an internal pullup. |+| 101 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 102 | TMS | input | JTAG test mode select input; has an internal pullup. |+| 103 | TRST | input | JTAG test reset input; has an internal pulldown. |+| 104 | DR0 | bidirectional | Serial port 0 data-receive input; high-impedance when SHZ or RESET is active. |+| 105 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 106 | FSR0 | bidirectional | Serial port 0 frame-synchronization pulse for receive, which initiates the data-receive process using DR0; high-impedance when SHZ or RESET is active. |+| 107 | CLKR0 | bidirectional | Serial port 0 receive serial shift clock; high-impedance when SHZ or RESET is active. |+| 108 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 109 | CLKX0 | bidirectional | Serial port 0 transmit serial shift clock; high-impedance when SHZ or RESET is active. |+| 110 | FSX0 | bidirectional | Serial port 0 frame-synchronization pulse for transmit, which initiates the data-transmit process using DX0; high-impedance when SHZ or RESET is active. |+| 111 | DX0 | bidirectional | Serial port 0 data-transmit output; high-impedance when SHZ or RESET is active. |+| 112 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 113 | TCLK1 | bidirectional | Timer 1 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 1; high-impedance when SHZ or RESET is active. |+| 114 | TCLK0 | bidirectional | Timer 0 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 0; high-impedance when SHZ or RESET is active. |+| 115 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 116 | XF1 | bidirectional | External flag 1, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active. |+| 117 | XF0 | bidirectional | External flag 0, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active. |+| 118 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 119 | INT3 | input | External interrupt 3 input. |+| 120 | INT2 | input | External interrupt 2 input. |+| 121 | INT1 | input | External interrupt 1 input. |+| 122 | INT0 | input | External interrupt 0 input. |+| 123 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 124 | EDGEMODE | input | Edge-mode input that enables interrupt edge-mode detection. |+| 125 | MCBL/MP | input | Microcomputer bootloader / microprocessor mode-select input. |+| 126 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 127 | RESET | input | Reset input: when low the device is held in reset, and when it returns high execution begins at the location given by the reset vector. |+| 128 | SHZ | input | Shutdown high-impedance input that places all pins in high-impedance when active; a low on SHZ corrupts device memory and register contents, so reset with SHZ high. |+| 129 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 130 | EXTCLK | input | External clock input, logic-level compatible; tie to ground if the XIN/XOUT oscillator is used. |+| 131 | PLLVDD | power_in | Internally isolated PLL supply; connect to CVDD (1.8 V). |+| 132 | XOUT | output | Clock output from the internal crystal oscillator; leave unconnected if a crystal is not used. |+| 133 | XIN | input | Clock input to the internal oscillator from a crystal; tie to ground if EXTCLK is used. |+| 134 | PLLVSS | power_in | Internally isolated PLL ground; connect to VSS. |+| 135 | CLKMD1 | input | Clock mode select pin 1. |+| 136 | CLKMD0 | input | Clock mode select pin 0. |+| 137 | CVDD | power_in | Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling). |+| 138 | RSV1 | input | Reserved pin; use an individual pullup to DVDD. |+| 139 | RSV0 | input | Reserved pin; use an individual pullup to DVDD. |+| 140 | VSS | power_in | Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane. |+| 141 | A23 | tri_state | 24-bit primary-bus address output bit A23; high-impedance when SHZ, HOLD, or RESET is active. |+| 142 | A22 | tri_state | 24-bit primary-bus address output bit A22; high-impedance when SHZ, HOLD, or RESET is active. |+| 143 | DVDD | power_in | Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling). |+| 144 | A21 | tri_state | 24-bit primary-bus address output bit A21; high-impedance when SHZ, HOLD, or RESET is active. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-144(20x20) |+| Category | Embedded Processors & Controllers |+| Pins | 144 |++## CAD (KiCad official)++- Symbol: `TMS320VC33PGE150`+- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`+- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)+- 3D model files: `tms320vc33pge150-etched.step` / `tms320vc33pge150-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320vc33pge150.step` / `tms320vc33pge150.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320vc33) (59 pp, sha256 `4e3387336ae8ae0f`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320vc33pge150-datasheet.pdf)
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high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "2",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "3",+ "name": "A19",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A19; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "4",+ "name": "A18",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A18; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "5",+ "name": "A17",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A17; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "6",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "7",+ "name": "A16",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A16; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "8",+ "name": "A15",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A15; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "9",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "10",+ "name": "A14",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A14; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "11",+ "name": "A13",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A13; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "12",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "13",+ "name": "A12",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A12; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "14",+ "name": "A11",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A11; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "15",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "16",+ "name": "A10",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A10; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "17",+ "name": "A9",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A9; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "18",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "19",+ "name": "A8",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A8; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "20",+ "name": "A7",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A7; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "21",+ "name": "A6",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A6; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "22",+ "name": "A5",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A5; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "23",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "24",+ "name": "A4",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A4; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "25",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "26",+ "name": "A3",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A3; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "27",+ "name": "A2",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A2; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "28",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "29",+ "name": "A1",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A1; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "30",+ "name": "A0",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A0; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "31",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "32",+ "name": "PAGE3",+ "type": "tri_state",+ "description": "Decoded page strobe 3 for external access; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "33",+ "name": "PAGE2",+ "type": "tri_state",+ "description": "Decoded page strobe 2 for external access; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "34",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "35",+ "name": "PAGE1",+ "type": "tri_state",+ "description": "Decoded page strobe 1 for external access; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "36",+ "name": "PAGE0",+ "type": "tri_state",+ "description": "Decoded page strobe 0 for external access; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "37",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "38",+ "name": "H1",+ "type": "tri_state",+ "description": "External H1 clock output; high-impedance when SHZ is active."+ },+ {+ "number": "39",+ "name": "H3",+ "type": "tri_state",+ "description": "External H3 clock output; high-impedance when SHZ is active."+ },+ {+ "number": "40",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "41",+ "name": "STRB",+ "type": "tri_state",+ "description": "Strobe output for all external accesses; high-impedance when SHZ or HOLD is active."+ },+ {+ "number": "42",+ "name": "R/W",+ "type": "tri_state",+ "description": "Read/write output: high for a read and low for a write over the parallel interface; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "43",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "44",+ "name": "IACK",+ "type": "tri_state",+ "description": "Interrupt acknowledge output generated by the IACK instruction, which can indicate when a section of code is executing; high-impedance when SHZ is active."+ },+ {+ "number": "45",+ "name": "RDY",+ "type": "input",+ "description": "Ready input indicating that the external device is prepared for transaction completion."+ },+ {+ "number": "46",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "47",+ "name": "HOLD",+ "type": "input",+ "description": "Hold input: when low, the ongoing transaction completes and the address, data, STRB and R/W outputs go high-impedance until HOLD returns high or the NOHOLD bit is set."+ },+ {+ "number": "48",+ "name": "HOLDA",+ "type": "tri_state",+ "description": "Hold acknowledge output asserted in response to a logic-low on HOLD, indicating the primary bus is high-impedance and transactions are held; high-impedance when SHZ is active."+ },+ {+ "number": "49",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "50",+ "name": "D31",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D31 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "51",+ "name": "D30",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D30 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "52",+ "name": "D29",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D29 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "53",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "54",+ "name": "D28",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D28 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "55",+ "name": "D27",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D27 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "56",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "57",+ "name": "D26",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D26 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "58",+ "name": "D25",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D25 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "59",+ "name": "D24",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D24 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "60",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "61",+ "name": "D23",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D23 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "62",+ "name": "D22",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D22 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "63",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "64",+ "name": "D21",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D21 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "65",+ "name": "D20",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D20 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "66",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "67",+ "name": "D19",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D19 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "68",+ "name": "D18",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D18 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "69",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "70",+ "name": "D17",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D17 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "71",+ "name": "D16",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D16 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "72",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "73",+ "name": "D15",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D15 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "74",+ "name": "D14",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D14 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "75",+ "name": "D13",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D13 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "76",+ "name": "D12",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D12 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "77",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "78",+ "name": "D11",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D11 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "79",+ "name": "D10",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D10 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "80",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "81",+ "name": "D9",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D9 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "82",+ "name": "D8",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D8 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "83",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "84",+ "name": "D7",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D7 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "85",+ "name": "D6",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D6 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "86",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "87",+ "name": "D5",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D5 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "88",+ "name": "D4",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D4 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "89",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "90",+ "name": "D3",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D3 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "91",+ "name": "D2",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D2 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "92",+ "name": "D1",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D1 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "93",+ "name": "D0",+ "type": "bidirectional",+ "description": "Primary-bus 32-bit data port bit D0 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "94",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "95",+ "name": "EMU1",+ "type": "bidirectional",+ "description": "JTAG emulation pin 1; use an individual pullup to DVDD."+ },+ {+ "number": "96",+ "name": "EMU0",+ "type": "bidirectional",+ "description": "JTAG emulation pin 0; use an individual pullup to DVDD."+ },+ {+ "number": "97",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "98",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input; has an internal pullup."+ },+ {+ "number": "99",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output."+ },+ {+ "number": "100",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input; has an internal pullup."+ },+ {+ "number": "101",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "102",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input; has an internal pullup."+ },+ {+ "number": "103",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset input; has an internal pulldown."+ },+ {+ "number": "104",+ "name": "DR0",+ "type": "bidirectional",+ "description": "Serial port 0 data-receive input; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "105",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "106",+ "name": "FSR0",+ "type": "bidirectional",+ "description": "Serial port 0 frame-synchronization pulse for receive, which initiates the data-receive process using DR0; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "107",+ "name": "CLKR0",+ "type": "bidirectional",+ "description": "Serial port 0 receive serial shift clock; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "108",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "109",+ "name": "CLKX0",+ "type": "bidirectional",+ "description": "Serial port 0 transmit serial shift clock; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "110",+ "name": "FSX0",+ "type": "bidirectional",+ "description": "Serial port 0 frame-synchronization pulse for transmit, which initiates the data-transmit process using DX0; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "111",+ "name": "DX0",+ "type": "bidirectional",+ "description": "Serial port 0 data-transmit output; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "112",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "113",+ "name": "TCLK1",+ "type": "bidirectional",+ "description": "Timer 1 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 1; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "114",+ "name": "TCLK0",+ "type": "bidirectional",+ "description": "Timer 0 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 0; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "115",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "116",+ "name": "XF1",+ "type": "bidirectional",+ "description": "External flag 1, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "117",+ "name": "XF0",+ "type": "bidirectional",+ "description": "External flag 0, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active."+ },+ {+ "number": "118",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "119",+ "name": "INT3",+ "type": "input",+ "description": "External interrupt 3 input."+ },+ {+ "number": "120",+ "name": "INT2",+ "type": "input",+ "description": "External interrupt 2 input."+ },+ {+ "number": "121",+ "name": "INT1",+ "type": "input",+ "description": "External interrupt 1 input."+ },+ {+ "number": "122",+ "name": "INT0",+ "type": "input",+ "description": "External interrupt 0 input."+ },+ {+ "number": "123",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "124",+ "name": "EDGEMODE",+ "type": "input",+ "description": "Edge-mode input that enables interrupt edge-mode detection."+ },+ {+ "number": "125",+ "name": "MCBL/MP",+ "type": "input",+ "description": "Microcomputer bootloader / microprocessor mode-select input."+ },+ {+ "number": "126",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "127",+ "name": "RESET",+ "type": "input",+ "description": "Reset input: when low the device is held in reset, and when it returns high execution begins at the location given by the reset vector."+ },+ {+ "number": "128",+ "name": "SHZ",+ "type": "input",+ "description": "Shutdown high-impedance input that places all pins in high-impedance when active; a low on SHZ corrupts device memory and register contents, so reset with SHZ high."+ },+ {+ "number": "129",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "130",+ "name": "EXTCLK",+ "type": "input",+ "description": "External clock input, logic-level compatible; tie to ground if the XIN/XOUT oscillator is used."+ },+ {+ "number": "131",+ "name": "PLLVDD",+ "type": "power_in",+ "description": "Internally isolated PLL supply; connect to CVDD (1.8 V)."+ },+ {+ "number": "132",+ "name": "XOUT",+ "type": "output",+ "description": "Clock output from the internal crystal oscillator; leave unconnected if a crystal is not used."+ },+ {+ "number": "133",+ "name": "XIN",+ "type": "input",+ "description": "Clock input to the internal oscillator from a crystal; tie to ground if EXTCLK is used."+ },+ {+ "number": "134",+ "name": "PLLVSS",+ "type": "power_in",+ "description": "Internally isolated PLL ground; connect to VSS."+ },+ {+ "number": "135",+ "name": "CLKMD1",+ "type": "input",+ "description": "Clock mode select pin 1."+ },+ {+ "number": "136",+ "name": "CLKMD0",+ "type": "input",+ "description": "Clock mode select pin 0."+ },+ {+ "number": "137",+ "name": "CVDD",+ "type": "power_in",+ "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."+ },+ {+ "number": "138",+ "name": "RSV1",+ "type": "input",+ "description": "Reserved pin; use an individual pullup to DVDD."+ },+ {+ "number": "139",+ "name": "RSV0",+ "type": "input",+ "description": "Reserved pin; use an individual pullup to DVDD."+ },+ {+ "number": "140",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."+ },+ {+ "number": "141",+ "name": "A23",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A23; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "142",+ "name": "A22",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A22; high-impedance when SHZ, HOLD, or RESET is active."+ },+ {+ "number": "143",+ "name": "DVDD",+ "type": "power_in",+ "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."+ },+ {+ "number": "144",+ "name": "A21",+ "type": "tri_state",+ "description": "24-bit primary-bus address output bit A21; high-impedance when SHZ, HOLD, or RESET is active."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package hint LQFP-144 (20x20) matches the datasheet PGE package: 144-pin low-profile quad flatpack, ; Speed/temperature variant: Table 8 lists TMS320VC33PGE150 at 0 to 90 C. The package addendum (page 5; The alphabetical terminal-assignment table on pages 4 is garbled in the text extraction, with some p"+ ],+ "pages_sent": 18,+ "cost_usd": 0.1947,+ "at": "2026-10-08T02:51:48"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320vc33",+ "pages": 59,+ "sha256": "4e3387336ae8ae0f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 144,+ "described": 144,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320vc33pge150.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 22,+ 22,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b4d698da8bb7697b754adb5655c932342462d9b9341cdaa081b3604dbdf7559b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320vc33pge150-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 22,+ 22,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d2b6046518f8f83dab66b2eb27e12a4262af126857ed708eac8d66b0046939d7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}