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TMS320LF2401AVFS

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320LF2401AVFS

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-32(7x7)

TMS320LF2401AVFS from Texas Instruments, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TMS/XF bidirectional JTAG test mode select input when TRST is high, otherwise a general-purpose external flag output (XF) set and reset by the SETC XF/CLRC XF instructions, with an internal pullup and XF enabled only after SCSR4 bit 0 is set by user code.
2 SCIRXD/IOPB4 bidirectional SCI asynchronous serial receive data input, or general-purpose I/O IOPB4 when the SCI function is not selected, with an internal pullup.
3 SCITXD/IOPB3 bidirectional SCI asynchronous serial transmit data output, or general-purpose I/O IOPB3, with an internal pullup.
4 TCK/IOPB1 bidirectional JTAG test clock when TRST is high, or general-purpose I/O IOPB1 when TRST is low, with an internal pullup.
5 VDD power_in Core supply voltage of 3.3 V.
6 XTAL1/CLKIN input Crystal or external clock input to the PLL, with input clock frequency of 4 MHz to 20 MHz and the CLK PS bits adjusted so CLKOUT is 40 MHz maximum.
7 XTAL2 output Crystal output of the on-chip oscillator.
8 VSS power_in Core ground.
9 RS bidirectional Device reset input that sets PC = 0 and starts execution at 0x0000 when driven high, and is driven low by the DSP for 128 CLKIN cycles during a watchdog reset; the output is open-drain with an internal pullup of about 20 µA and external drive by an open-drain device is recommended.
10 PWM4/IOPA4 bidirectional Compare/PWM output 4 or general-purpose I/O IOPA4, with an internal pullup.
11 PWM5/IOPA5 bidirectional Compare/PWM output 5 or general-purpose I/O IOPA5, with an internal pullup.
12 PWM6/IOPA6 bidirectional Compare/PWM output 6 or general-purpose I/O IOPA6, with an internal pullup.
13 ADCIN04 input Analog input channel 4 of the 10-bit ADC.
14 ADCIN03 input Analog input channel 3 of the 10-bit ADC.
15 ADCIN02 input Analog input channel 2 of the 10-bit ADC.
16 ADCIN01 input Analog input channel 1 of the 10-bit ADC.
17 ADCIN00 input Analog input channel 0 of the 10-bit ADC.
18 VSSA power_in Analog ground reference for the ADC, internally connected to VREFLO, which should be isolated from digital ground for ADC accuracy and noise immunity.
19 VCCA power_in Analog supply voltage for the ADC of 3.3 V, internally connected to VREFHI, which should be isolated from the digital supply for ADC accuracy and noise immunity.
20 TRST input JTAG test reset, an active-high test pin with an internal pulldown that must be kept low during normal operation, and should not be driven through pullup resistors.
21 VSS power_in Core ground.
22 XINT2/ADCSOC/CAP1/IOPA7/CLKOUT bidirectional Multiplexed external interrupt XINT2, ADC start-of-conversion, capture input CAP1, general-purpose I/O IOPA7, or CPU clock output CLKOUT when MCRA bit 7 is set, with an internal pullup.
23 TDO/IOPB2 bidirectional JTAG scan data output TDO when TRST is high, or general-purpose I/O IOPB2 when TRST is low, with an internal pulldown.
24 TDI/OPB5 bidirectional JTAG test data input when TRST is high, or general-purpose output OPB5 when TRST is low; this pin must be held low during reset to invoke the on-chip boot ROM, and it is forced high-impedance while RS is low.
25 VDD power_in Core supply voltage of 3.3 V.
26 VCCP power_in Flash programming supply that must be connected to a 5-V supply for Flash programming and must not be left floating or tied through a current-limiting resistor; it is a no-connect on ROM (LC2401A) parts.
27 PWM1/IOPA1 bidirectional Compare/PWM output 1 or general-purpose I/O IOPA1, with an internal pullup.
28 PWM2/IOPA2 bidirectional Compare/PWM output 2 or general-purpose I/O IOPA2, with an internal pullup.
29 PWM3/IOPA3 bidirectional Compare/PWM output 3 or general-purpose I/O IOPA3, with an internal pullup.
30 VSS power_in Core ground.
31 T2PWM/XINT1/IOPB0 bidirectional Multiplexed pin that comes up as external interrupt XINT1/IOPB0 after reset, with T2PWM selected by MCRA bit 8, and with an internal pullup.
32 PDPINTA/IOPA0 bidirectional Power drive protection input that, when pulled low externally, generates an interrupt and forces all PWM outputs to high impedance even when the DSP is not executing, with an internal pullup and a requirement to be held high when the boot ROM is invoked.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: TMS320LF2401AVFS
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: tms320lf2401avfs-etched.step / tms320lf2401avfs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320lf2401avfs.step / tms320lf2401avfs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (91 pp, sha256 3382e0cf5f319c75, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF