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TMS320F28335PTPS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerstms320f28335ptpsfactory-2.0.0extractor-text

Verified TMS320F28335PTPS

by Ray · last 5 Nov 2026 · 1 record · files match
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Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 176 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TMS320F28335PTPS · LQFP-176(24x24) · 176 pins
  • ✓copper: 176 copper pads, none touching another net
  • ✓datasheet: all 176 pin names found in the 219-page datasheet
  • ✓distributor: lcsc C97670, digikey 296-36015-ND, mouser 595-TMS320F28335PTPS
  • ✓family: LQFP-176_24x24mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-24_luq6u/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 176 pins = 176 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 176 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tms320f28335ptps.kicad_sym✓ tms320f28335ptps.kicad_mod✓ tms320f28335ptps.step
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Contents

README

markdown

TMS320F28335PTPS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)

TMS320F28335PTPS from Texas Instruments, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
78 TRST input JTAG test reset with internal pulldown; must be held low during normal operation with an external pulldown resistor (2.2 kOhm generally adequate).
87 TCK input JTAG test clock input with internal pullup.
79 TMS input JTAG test-mode select input with internal pullup, clocked into the TAP controller on the rising edge of TCK.
76 TDI input JTAG test data input with internal pullup, clocked into the selected register on a rising edge of TCK.
77 TDO output JTAG scan test data output, shifted out on the falling edge of TCK (O/Z, 8 mA drive).
85 EMU0 bidirectional Emulator pin 0 used as JTAG debug probe interrupt and boundary-scan mode select; requires an external 2.2-kOhm to 4.7-kOhm pullup (I/O/Z, 8 mA drive).
86 EMU1 bidirectional Emulator pin 1 used as JTAG debug probe interrupt and boundary-scan mode select; requires an external 2.2-kOhm to 4.7-kOhm pullup (I/O/Z, 8 mA drive).
84 VDD3VFL power_in 3.3-V flash core power pin that must be connected to 3.3 V at all times.
81 TEST1 bidirectional Reserved for TI test; must be left unconnected.
82 TEST2 bidirectional Reserved for TI test; must be left unconnected.
138 XCLKOUT output Output clock derived from SYSCLKOUT, at reset equal to SYSCLKOUT/4; not placed in high impedance during reset (O/Z, 8 mA drive).
105 XCLKIN input External oscillator input for a 3.3-V clock source; must be tied to GND when a crystal/resonator or 1.9-V oscillator on X1 is used.
104 X1 input Internal oscillator input (crystal/resonator across X1 and X2) or 1.9-V/1.8-V external oscillator input referenced to the core supply.
102 X2 output Internal oscillator output for a crystal or ceramic resonator across X1 and X2; left unconnected if unused.
80 XRS bidirectional Device reset input and watchdog reset output, open drain with internal pullup, driven low for 512 OSCCLK cycles during watchdog reset (I/OD).
35 ADCINA7 input ADC Group A channel 7 analog input, 0 to 3 V with respect to ADCLO.
36 ADCINA6 input ADC Group A channel 6 analog input, 0 to 3 V with respect to ADCLO.
37 ADCINA5 input ADC Group A channel 5 analog input, 0 to 3 V with respect to ADCLO.
38 ADCINA4 input ADC Group A channel 4 analog input, 0 to 3 V with respect to ADCLO.
39 ADCINA3 input ADC Group A channel 3 analog input, 0 to 3 V with respect to ADCLO.
40 ADCINA2 input ADC Group A channel 2 analog input, 0 to 3 V with respect to ADCLO.
41 ADCINA1 input ADC Group A channel 1 analog input, 0 to 3 V with respect to ADCLO.
42 ADCINA0 input ADC Group A channel 0 analog input, 0 to 3 V with respect to ADCLO.
53 ADCINB7 input ADC Group B channel 7 analog input, 0 to 3 V with respect to ADCLO.
52 ADCINB6 input ADC Group B channel 6 analog input, 0 to 3 V with respect to ADCLO.
51 ADCINB5 input ADC Group B channel 5 analog input, 0 to 3 V with respect to ADCLO.
50 ADCINB4 input ADC Group B channel 4 analog input, 0 to 3 V with respect to ADCLO.
49 ADCINB3 input ADC Group B channel 3 analog input, 0 to 3 V with respect to ADCLO.
48 ADCINB2 input ADC Group B channel 2 analog input, 0 to 3 V with respect to ADCLO.
47 ADCINB1 input ADC Group B channel 1 analog input, 0 to 3 V with respect to ADCLO.
46 ADCINB0 input ADC Group B channel 0 analog input, 0 to 3 V with respect to ADCLO.
43 ADCLO input ADC low reference, connect to analog ground.
57 ADCRESEXT passive ADC external current bias resistor pin; connect a 22-kOhm resistor to analog ground.
54 ADCREFIN input ADC external reference input.
56 ADCREFP output ADC internal positive reference output; requires a low-ESR (under 1.5 Ohm) 2.2 uF ceramic bypass capacitor to analog ground.
55 ADCREFM output ADC internal medium reference output; requires a low-ESR (under 1.5 Ohm) 2.2 uF ceramic bypass capacitor to analog ground.
34 VDDA2 power_in ADC analog power pin (3.3 V).
33 VSSA2 power_in ADC analog ground pin.
45 VDDAIO power_in ADC analog I/O power pin (3.3 V).
44 VSSAIO power_in ADC analog I/O ground pin.
31 VDD1A18 power_in ADC analog power pin (1.9 V/1.8 V).
32 VSS1AGND power_in ADC analog ground pin.
59 VDD2A18 power_in ADC analog power pin (1.9 V/1.8 V).
58 VSS2AGND power_in ADC analog ground pin.
4 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
15 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
23 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
29 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
61 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
101 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
109 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
117 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
126 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
139 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
146 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
154 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
167 VDD power_in CPU and logic digital power pin (1.9-V/1.8-V core supply).
9 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
71 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
93 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
107 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
121 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
143 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
159 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
170 VDDIO power_in Digital I/O power pin (3.3-V I/O supply).
3 VSS power_in Digital ground pin.
8 VSS power_in Digital ground pin.
14 VSS power_in Digital ground pin.
22 VSS power_in Digital ground pin.
30 VSS power_in Digital ground pin.
60 VSS power_in Digital ground pin.
70 VSS power_in Digital ground pin.
83 VSS power_in Digital ground pin.
92 VSS power_in Digital ground pin.
103 VSS power_in Digital ground pin.
106 VSS power_in Digital ground pin.
108 VSS power_in Digital ground pin.
118 VSS power_in Digital ground pin.
120 VSS power_in Digital ground pin.
125 VSS power_in Digital ground pin.
140 VSS power_in Digital ground pin.
144 VSS power_in Digital ground pin.
147 VSS power_in Digital ground pin.
155 VSS power_in Digital ground pin.
160 VSS power_in Digital ground pin.
166 VSS power_in Digital ground pin.
171 VSS power_in Digital ground pin.
5 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (I/O/Z) with EPWM1A and HRPWM channel output; internal pullup not enabled at reset.
6 GPIO1/EPWM1B/ECAP6/MFSRB bidirectional General-purpose I/O 1 (I/O/Z) with EPWM1B, ECAP6 and McBSP-B receive frame sync; internal pullup not enabled at reset.
7 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (I/O/Z) with EPWM2A and HRPWM channel output; internal pullup not enabled at reset.
10 GPIO3/EPWM2B/ECAP5/MCLKRB bidirectional General-purpose I/O 3 (I/O/Z) with EPWM2B, ECAP5 and McBSP-B receive clock; internal pullup not enabled at reset.
11 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (I/O/Z) with EPWM3A and HRPWM channel output; internal pullup not enabled at reset.
12 GPIO5/EPWM3B/MFSRA/ECAP1 bidirectional General-purpose I/O 5 (I/O/Z) with EPWM3B, McBSP-A receive frame sync and ECAP1; internal pullup not enabled at reset.
13 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (I/O/Z) with EPWM4A and HRPWM output and external ePWM sync input/output; internal pullup not enabled at reset.
16 GPIO7/EPWM4B/MCLKRA/ECAP2 bidirectional General-purpose I/O 7 (I/O/Z) with EPWM4B, McBSP-A receive clock and ECAP2; internal pullup enabled at reset.
17 GPIO8/EPWM5A/CANTXB/ADCSOCAO bidirectional General-purpose I/O 8 (I/O/Z) with EPWM5A and HRPWM output, CAN-B transmit and ADC start-of-conversion A; internal pullup enabled at reset.
18 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional General-purpose I/O 9 (I/O/Z) with EPWM5B, SCI-B transmit and ECAP3; internal pullup enabled at reset.
19 GPIO10/EPWM6A/CANRXB/ADCSOCBO bidirectional General-purpose I/O 10 (I/O/Z) with EPWM6A and HRPWM output, CAN-B receive and ADC start-of-conversion B; internal pullup enabled at reset.
20 GPIO11/EPWM6B/SCIRXDB/ECAP4 bidirectional General-purpose I/O 11 (I/O/Z) with EPWM6B, SCI-B receive and ECAP4; internal pullup enabled at reset.
21 GPIO12/TZ1/CANTXB/MDXB bidirectional General-purpose I/O 12 (I/O/Z) with Trip Zone input 1, CAN-B transmit and McBSP-B transmit data; internal pullup enabled at reset.
24 GPIO13/TZ2/CANRXB/MDRB bidirectional General-purpose I/O 13 (I/O/Z) with Trip Zone input 2, CAN-B receive and McBSP-B receive data; internal pullup enabled at reset.
25 GPIO14/TZ3/XHOLD/SCITXDB/MCLKXB bidirectional General-purpose I/O 14 (I/O/Z) with Trip Zone input 3, external hold request XHOLD (active low), SCI-B transmit and McBSP-B transmit clock; internal pullup enabled at reset.
26 GPIO15/TZ4/XHOLDA/SCIRXDB/MFSXB bidirectional General-purpose I/O 15 (I/O/Z) with Trip Zone input 4, external hold acknowledge XHOLDA (active low), SCI-B receive and McBSP-B transmit frame sync; internal pullup enabled at reset.
27 GPIO16/SPISIMOA/CANTXB/TZ5 bidirectional General-purpose I/O 16 (I/O/Z) with SPI-A slave in/master out, CAN-B transmit and Trip Zone input 5; internal pullup enabled at reset.
28 GPIO17/SPISOMIA/CANRXB/TZ6 bidirectional General-purpose I/O 17 (I/O/Z) with SPI-A slave out/master in, CAN-B receive and Trip Zone input 6; internal pullup enabled at reset.
62 GPIO18/SPICLKA/SCITXDB/CANRXA bidirectional General-purpose I/O 18 (I/O/Z) with SPI-A clock, SCI-B transmit and CAN-A receive; internal pullup enabled at reset.
63 GPIO19/SPISTEA/SCIRXDB/CANTXA bidirectional General-purpose I/O 19 (I/O/Z) with SPI-A slave transmit enable, SCI-B receive and CAN-A transmit; internal pullup enabled at reset.
64 GPIO20/EQEP1A/MDXA/CANTXB bidirectional General-purpose I/O 20 (I/O/Z) with Enhanced QEP1 input A, McBSP-A transmit data and CAN-B transmit; internal pullup enabled at reset.
65 GPIO21/EQEP1B/MDRA/CANRXB bidirectional General-purpose I/O 21 (I/O/Z) with Enhanced QEP1 input B, McBSP-A receive data and CAN-B receive; internal pullup enabled at reset.
66 GPIO22/EQEP1S/MCLKXA/SCITXDB bidirectional General-purpose I/O 22 (I/O/Z) with Enhanced QEP1 strobe, McBSP-A transmit clock and SCI-B transmit; internal pullup enabled at reset.
67 GPIO23/EQEP1I/MFSXA/SCIRXDB bidirectional General-purpose I/O 23 (I/O/Z) with Enhanced QEP1 index, McBSP-A transmit frame sync and SCI-B receive; internal pullup enabled at reset.
68 GPIO24/ECAP1/EQEP2A/MDXB bidirectional General-purpose I/O 24 (I/O/Z) with Enhanced capture 1, Enhanced QEP2 input A and McBSP-B transmit data; internal pullup enabled at reset.
69 GPIO25/ECAP2/EQEP2B/MDRB bidirectional General-purpose I/O 25 (I/O/Z) with Enhanced capture 2, Enhanced QEP2 input B and McBSP-B receive data; internal pullup enabled at reset.
72 GPIO26/ECAP3/EQEP2I/MCLKXB bidirectional General-purpose I/O 26 (I/O/Z) with Enhanced capture 3, Enhanced QEP2 index and McBSP-B transmit clock; internal pullup enabled at reset.
73 GPIO27/ECAP4/EQEP2S/MFSXB bidirectional General-purpose I/O 27 (I/O/Z) with Enhanced capture 4, Enhanced QEP2 strobe and McBSP-B transmit frame sync; internal pullup enabled at reset.
141 GPIO28/SCIRXDA/XZCS6 bidirectional General-purpose I/O 28 (I/O/Z) with SCI-A receive data and XINTF zone 6 chip select; internal pullup enabled at reset.
2 GPIO29/SCITXDA/XA19 bidirectional General-purpose I/O 29 (I/O/Z) with SCI-A transmit data and XINTF address line 19; internal pullup enabled at reset.
1 GPIO30/CANRXA/XA18 bidirectional General-purpose I/O 30 (I/O/Z) with Enhanced CAN-A receive and XINTF address line 18; internal pullup enabled at reset.
176 GPIO31/CANTXA/XA17 bidirectional General-purpose I/O 31 (I/O/Z) with Enhanced CAN-A transmit and XINTF address line 17; internal pullup enabled at reset.
74 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 (I/O/Z) with I2C data open-drain bidirectional port, ePWM sync input and ADC start-of-conversion A; internal pullup enabled at reset.
75 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 (I/O/Z) with I2C clock open-drain bidirectional port, ePWM sync output and ADC start-of-conversion B; internal pullup enabled at reset.
142 GPIO34/ECAP1/XREADY bidirectional General-purpose I/O 34 (I/O/Z) with Enhanced capture 1 and XINTF Ready signal, which is always connected to the XINTF; internal pullup enabled at reset.
148 GPIO35/SCITXDA/XR/W bidirectional General-purpose I/O 35 (I/O/Z) with SCI-A transmit data and XINTF read-not-write strobe; internal pullup enabled at reset.
145 GPIO36/SCIRXDA/XZCS0 bidirectional General-purpose I/O 36 (I/O/Z) with SCI-A receive data and XINTF zone 0 chip select; internal pullup enabled at reset.
150 GPIO37/ECAP2/XZCS7 bidirectional General-purpose I/O 37 (I/O/Z) with Enhanced capture 2 and XINTF zone 7 chip select; internal pullup enabled at reset.
137 GPIO38/XWE0 bidirectional General-purpose I/O 38 (I/O/Z) with XINTF write enable 0 output; internal pullup enabled at reset.
175 GPIO39/XA16 bidirectional General-purpose I/O 39 (I/O/Z) with XINTF address line 16 output; internal pullup enabled at reset.
151 GPIO40/XA0/XWE1 bidirectional General-purpose I/O 40 (I/O/Z) with XINTF address line 0 or write enable 1 output; internal pullup enabled at reset.
152 GPIO41/XA1 bidirectional General-purpose I/O 41 (I/O/Z) with XINTF address line 1 output; internal pullup enabled at reset.
153 GPIO42/XA2 bidirectional General-purpose I/O 42 (I/O/Z) with XINTF address line 2 output; internal pullup enabled at reset.
156 GPIO43/XA3 bidirectional General-purpose I/O 43 (I/O/Z) with XINTF address line 3 output; internal pullup enabled at reset.
157 GPIO44/XA4 bidirectional General-purpose I/O 44 (I/O/Z) with XINTF address line 4 output; internal pullup enabled at reset.
158 GPIO45/XA5 bidirectional General-purpose I/O 45 (I/O/Z) with XINTF address line 5 output; internal pullup enabled at reset.
161 GPIO46/XA6 bidirectional General-purpose I/O 46 (I/O/Z) with XINTF address line 6 output; internal pullup enabled at reset.
162 GPIO47/XA7 bidirectional General-purpose I/O 47 (I/O/Z) with XINTF address line 7 output; internal pullup enabled at reset.
88 GPIO48/ECAP5/XD31 bidirectional General-purpose I/O 48 (I/O/Z) with Enhanced capture 5 and XINTF data line 31; internal pullup enabled at reset.
89 GPIO49/ECAP6/XD30 bidirectional General-purpose I/O 49 (I/O/Z) with Enhanced capture 6 and XINTF data line 30; internal pullup enabled at reset.
90 GPIO50/EQEP1A/XD29 bidirectional General-purpose I/O 50 (I/O/Z) with Enhanced QEP1 input A and XINTF data line 29; internal pullup enabled at reset.
91 GPIO51/EQEP1B/XD28 bidirectional General-purpose I/O 51 (I/O/Z) with Enhanced QEP1 input B and XINTF data line 28; internal pullup enabled at reset.
94 GPIO52/EQEP1S/XD27 bidirectional General-purpose I/O 52 (I/O/Z) with Enhanced QEP1 strobe and XINTF data line 27; internal pullup enabled at reset.
95 GPIO53/EQEP1I/XD26 bidirectional General-purpose I/O 53 (I/O/Z) with Enhanced QEP1 index and XINTF data line 26; internal pullup enabled at reset.
96 GPIO54/SPISIMOA/XD25 bidirectional General-purpose I/O 54 (I/O/Z) with SPI-A slave in/master out and XINTF data line 25; internal pullup enabled at reset.
97 GPIO55/SPISOMIA/XD24 bidirectional General-purpose I/O 55 (I/O/Z) with SPI-A slave out/master in and XINTF data line 24; internal pullup enabled at reset.
98 GPIO56/SPICLKA/XD23 bidirectional General-purpose I/O 56 (I/O/Z) with SPI-A clock and XINTF data line 23; internal pullup enabled at reset.
99 GPIO57/SPISTEA/XD22 bidirectional General-purpose I/O 57 (I/O/Z) with SPI-A slave transmit enable and XINTF data line 22; internal pullup enabled at reset.
100 GPIO58/MCLKRA/XD21 bidirectional General-purpose I/O 58 (I/O/Z) with McBSP-A receive clock and XINTF data line 21; internal pullup enabled at reset.
110 GPIO59/MFSRA/XD20 bidirectional General-purpose I/O 59 (I/O/Z) with McBSP-A receive frame sync and XINTF data line 20; internal pullup enabled at reset.
111 GPIO60/MCLKRB/XD19 bidirectional General-purpose I/O 60 (I/O/Z) with McBSP-B receive clock and XINTF data line 19; internal pullup enabled at reset.
112 GPIO61/MFSRB/XD18 bidirectional General-purpose I/O 61 (I/O/Z) with McBSP-B receive frame sync and XINTF data line 18; internal pullup enabled at reset.
113 GPIO62/SCIRXDC/XD17 bidirectional General-purpose I/O 62 (I/O/Z) with SCI-C receive data and XINTF data line 17; internal pullup enabled at reset.
114 GPIO63/SCITXDC/XD16 bidirectional General-purpose I/O 63 (I/O/Z) with SCI-C transmit data and XINTF data line 16; internal pullup enabled at reset.
115 GPIO64/XD15 bidirectional General-purpose I/O 64 (I/O/Z) with XINTF data line 15; internal pullup enabled at reset.
116 GPIO65/XD14 bidirectional General-purpose I/O 65 (I/O/Z) with XINTF data line 14; internal pullup enabled at reset.
119 GPIO66/XD13 bidirectional General-purpose I/O 66 (I/O/Z) with XINTF data line 13; internal pullup enabled at reset.
122 GPIO67/XD12 bidirectional General-purpose I/O 67 (I/O/Z) with XINTF data line 12; internal pullup enabled at reset.
123 GPIO68/XD11 bidirectional General-purpose I/O 68 (I/O/Z) with XINTF data line 11; internal pullup enabled at reset.
124 GPIO69/XD10 bidirectional General-purpose I/O 69 (I/O/Z) with XINTF data line 10; internal pullup enabled at reset.
127 GPIO70/XD9 bidirectional General-purpose I/O 70 (I/O/Z) with XINTF data line 9; internal pullup enabled at reset.
128 GPIO71/XD8 bidirectional General-purpose I/O 71 (I/O/Z) with XINTF data line 8; internal pullup enabled at reset.
129 GPIO72/XD7 bidirectional General-purpose I/O 72 (I/O/Z) with XINTF data line 7; internal pullup enabled at reset.
130 GPIO73/XD6 bidirectional General-purpose I/O 73 (I/O/Z) with XINTF data line 6; internal pullup enabled at reset.
131 GPIO74/XD5 bidirectional General-purpose I/O 74 (I/O/Z) with XINTF data line 5; internal pullup enabled at reset.
132 GPIO75/XD4 bidirectional General-purpose I/O 75 (I/O/Z) with XINTF data line 4; internal pullup enabled at reset.
133 GPIO76/XD3 bidirectional General-purpose I/O 76 (I/O/Z) with XINTF data line 3; internal pullup enabled at reset.
134 GPIO77/XD2 bidirectional General-purpose I/O 77 (I/O/Z) with XINTF data line 2; internal pullup enabled at reset.
135 GPIO78/XD1 bidirectional General-purpose I/O 78 (I/O/Z) with XINTF data line 1; internal pullup enabled at reset.
136 GPIO79/XD0 bidirectional General-purpose I/O 79 (I/O/Z) with XINTF data line 0; internal pullup enabled at reset.
163 GPIO80/XA8 bidirectional General-purpose I/O 80 (I/O/Z) with XINTF address line 8 output; internal pullup enabled at reset.
164 GPIO81/XA9 bidirectional General-purpose I/O 81 (I/O/Z) with XINTF address line 9 output; internal pullup enabled at reset.
165 GPIO82/XA10 bidirectional General-purpose I/O 82 (I/O/Z) with XINTF address line 10 output; internal pullup enabled at reset.
168 GPIO83/XA11 bidirectional General-purpose I/O 83 (I/O/Z) with XINTF address line 11 output; internal pullup enabled at reset.
169 GPIO84/XA12 bidirectional General-purpose I/O 84 (I/O/Z) with XINTF address line 12 output; internal pullup enabled at reset.
172 GPIO85/XA13 bidirectional General-purpose I/O 85 (I/O/Z) with XINTF address line 13 output; internal pullup enabled at reset.
173 GPIO86/XA14 bidirectional General-purpose I/O 86 (I/O/Z) with XINTF address line 14 output; internal pullup enabled at reset.
174 GPIO87/XA15 bidirectional General-purpose I/O 87 (I/O/Z) with XINTF address line 15 output; internal pullup enabled at reset.
149 XRD output External interface read enable strobe for the XINTF.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-176(24x24)
Category Embedded Processors & Controllers
Pins 176

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PCT TBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1 / 1 Time Base Period Register Set CMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1 / 0 Counter Compare Control Register 120

CAD (KiCad official)

  • Symbol: TMS320F28335PTPS
  • Footprint: Package_QFP:LQFP-176_24x24mm_P0.5mm
  • 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
  • 3D model files: tms320f28335ptps-etched.step / tms320f28335ptps-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28335ptps.step / tms320f28335ptps.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (219 pp, sha256 623049df7ad5c55a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF