component
TMS320F28333PGFA
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28333PGFA
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)
TMS320F28333PGFA from Texas Instruments, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO30/CANRXA/XA18 | bidirectional | General-purpose I/O 30 (I/O/Z); alternates are eCAN-A receive (input) and external interface address line 18 (output). |
| 2 | GPIO29/SCITXDA/XA19 | bidirectional | General-purpose I/O 29 (I/O/Z); alternates are SCI-A transmit data (output) and external interface address line 19 (output). |
| 3 | VSS | power_in | Digital ground pin (0 V reference). |
| 4 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 5 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 (I/O/Z), pull-up disabled at reset; alternate is ePWM1 output A and HRPWM channel (output). |
| 6 | GPIO1/EPWM1B/ECAP6/MFSRB | bidirectional | General-purpose I/O 1 (I/O/Z), pull-up disabled at reset; alternates are ePWM1 output B (output), eCAP6 input/output, and McBSP-B receive frame sync (I/O). |
| 7 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 (I/O/Z), pull-up disabled at reset; alternate is ePWM2 output A and HRPWM channel (output). |
| 8 | VSS | power_in | Digital ground pin (0 V reference). |
| 9 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 10 | GPIO3/EPWM2B/ECAP5/MCLKRB | bidirectional | General-purpose I/O 3 (I/O/Z), pull-up disabled at reset; alternates are ePWM2 output B (output), eCAP5 input/output, and McBSP-B receive clock (I/O). |
| 11 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 (I/O/Z), pull-up disabled at reset; alternate is ePWM3 output A and HRPWM channel (output). |
| 12 | GPIO5/EPWM3B/MFSRA/ECAP1 | bidirectional | General-purpose I/O 5 (I/O/Z), pull-up disabled at reset; alternates are ePWM3 output B (output), McBSP-B receive frame sync (I/O), and eCAP1 input/output. |
| 13 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 (I/O/Z), pull-up disabled at reset; alternates are ePWM4 output A and HRPWM channel (output), external ePWM sync pulse input (input), and external ePWM sync pulse output (output). |
| 14 | VSS | power_in | Digital ground pin (0 V reference). |
| 15 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 16 | GPIO7/EPWM4B/MCLKRA/ECAP2 | bidirectional | General-purpose I/O 7 (I/O/Z), pull-up disabled at reset; alternates are ePWM4 output B (output), McBSP-A receive clock (I/O), and eCAP2 input/output. |
| 17 | GPIO8/EPWM5A/CANTXB/ADCSOCAO | bidirectional | General-purpose I/O 8 (I/O/Z), pull-up disabled at reset; alternates are ePWM5 output A and HRPWM channel (output), eCAN-B transmit (output), and ADC start-of-conversion A (output). |
| 18 | GPIO9/EPWM5B/SCITXDB/ECAP3 | bidirectional | General-purpose I/O 9 (I/O/Z), pull-up disabled at reset; alternates are ePWM5 output B (output), SCI-B transmit data (output), and eCAP3 input/output. |
| 19 | GPIO10/EPWM6A/CANRXB/ADCSOCBO | bidirectional | General-purpose I/O 10 (I/O/Z), pull-up disabled at reset; alternates are ePWM6 output A and HRPWM channel (output), eCAN-B receive (input), and ADC start-of-conversion B (output). |
| 20 | GPIO11/EPWM6B/SCIRXDB/ECAP4 | bidirectional | General-purpose I/O 11 (I/O/Z), pull-up disabled at reset; alternates are ePWM6 output B (output), SCI-B receive data (I/O), and eCAP4 input/output. |
| 21 | GPIO12 | bidirectional | General-purpose I/O 12 (I/O/Z); alternates are trip-zone input 1 (input), eCAN-B transmit (output), and McBSP-B transmit serial data (output). |
| 22 | VSS | power_in | Digital ground pin (0 V reference). |
| 23 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 24 | GPIO13 | bidirectional | General-purpose I/O 13 (I/O/Z); alternates are trip-zone input 2 (input), eCAN-B receive (input), and McBSP-B receive serial data (input). |
| 25 | GPIO14 | bidirectional | General-purpose I/O 14 (I/O/Z); alternates are trip-zone input 3 (input), XINTF external hold request XHOLD (input, active low, which releases the external bus when asserted), SCI-B transmit (output), and McBSP-B transmit clock (I/O). |
| 26 | GPIO15 | bidirectional | General-purpose I/O 15 (I/O/Z); the TZ4 function is selected when configured as input and XHOLDA (output, active low hold acknowledge) when configured as output; other alternates are SCI-B receive (input) and McBSP-B transmit frame sync (I/O). |
| 27 | GPIO16/SPISIMOA/CANTXB/TZ5 | bidirectional | General-purpose I/O 16 (I/O/Z); alternates are SPI-A slave-in/master-out (I/O), eCAN-B transmit (output), and trip-zone input 5 (input). |
| 28 | GPIO17/SPISOMIA/CANRXB/TZ6 | bidirectional | General-purpose I/O 17 (I/O/Z); alternates are SPI-A slave-out/master-in (I/O), eCAN-B receive (input), and trip-zone input 6 (input). |
| 29 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 30 | VSS | power_in | Digital ground pin (0 V reference). |
| 31 | VDD1A18 | power_in | ADC analog core supply; 1.71 V to 1.89 V (1.8 V nominal) at 100 MHz. |
| 32 | VSS1AGND | power_in | ADC analog ground pin (0 V reference). |
| 33 | VSSA2 | power_in | ADC analog ground pin (0 V reference). |
| 34 | VDDA2 | power_in | ADC analog supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 35 | ADCINA7 | input | ADC group A, channel 7 analog input (0 V to 3 V with respect to ADCLO). |
| 36 | ADCINA6 | input | ADC group A, channel 6 analog input (0 V to 3 V with respect to ADCLO). |
| 37 | ADCINA5 | input | ADC group A, channel 5 analog input (0 V to 3 V with respect to ADCLO). |
| 38 | ADCINA4 | input | ADC group A, channel 4 analog input (0 V to 3 V with respect to ADCLO). |
| 39 | ADCINA3 | input | ADC group A, channel 3 analog input (0 V to 3 V with respect to ADCLO). |
| 40 | ADCINA2 | input | ADC group A, channel 2 analog input (0 V to 3 V with respect to ADCLO). |
| 41 | ADCINA1 | input | ADC group A, channel 1 analog input (0 V to 3 V with respect to ADCLO). |
| 42 | ADCINA0 | input | ADC group A, channel 0 analog input (0 V to 3 V with respect to ADCLO). |
| 43 | ADCLO | input | ADC low reference, connected to analog ground. |
| 44 | VSSAIO | power_in | ADC analog I/O ground pin (0 V reference). |
| 45 | VDDAIO | power_in | ADC analog I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 46 | ADCINB0 | input | ADC group B, channel 0 analog input (0 V to 3 V with respect to ADCLO). |
| 47 | ADCINB1 | input | ADC group B, channel 1 analog input (0 V to 3 V with respect to ADCLO). |
| 48 | ADCINB2 | input | ADC group B, channel 2 analog input (0 V to 3 V with respect to ADCLO). |
| 49 | ADCINB3 | input | ADC group B, channel 3 analog input (0 V to 3 V with respect to ADCLO). |
| 50 | ADCINB4 | input | ADC group B, channel 4 analog input (0 V to 3 V with respect to ADCLO). |
| 51 | ADCINB5 | input | ADC group B, channel 5 analog input (0 V to 3 V with respect to ADCLO). |
| 52 | ADCINB6 | input | ADC group B, channel 6 analog input (0 V to 3 V with respect to ADCLO). |
| 53 | ADCINB7 | input | ADC group B, channel 7 analog input (0 V to 3 V with respect to ADCLO). |
| 54 | ADCREFIN | input | External ADC reference input; the datasheet specifies 1.024 V, 1.500 V or 2.048 V from a precision source when used. |
| 55 | ADCREFM | output | Internal ADC reference medium output; requires a 2.2 µF ceramic bypass capacitor with ESR below 1.5 Ω to analog ground. |
| 56 | ADCREFP | output | Internal ADC reference positive output; requires a 2.2 µF ceramic bypass capacitor with ESR below 1.5 Ω to analog ground. |
| 57 | ADCRESEXT | passive | ADC external current bias resistor pin; a 22 kΩ resistor must be connected to analog ground. |
| 58 | VSS2AGND | power_in | ADC analog ground pin (0 V reference). |
| 59 | VDD2A18 | power_in | ADC analog core supply; 1.71 V to 1.89 V (1.8 V nominal) at 100 MHz. |
| 60 | VSS | power_in | Digital ground pin (0 V reference). |
| 61 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 62 | GPIO18/SPICLKA/SCITXDB/CANRXA | bidirectional | General-purpose I/O 18 (I/O/Z); alternates are SPI-A clock (I/O), SCI-B transmit (output), and eCAN-A receive (input). |
| 63 | GPIO19 | bidirectional | General-purpose I/O 19 (I/O/Z); alternates are SPI-A slave transmit enable (I/O), SCI-B receive (input), and eCAN-A transmit (output). |
| 64 | GPIO20/EQEP1A/MDXA/CANTXB | bidirectional | General-purpose I/O 20 (I/O/Z); alternates are eQEP1 input A (input), McBSP-A transmit serial data (output), and eCAN-B transmit (output). |
| 65 | GPIO21/EQEP1B/MDRA/CANRXB | bidirectional | General-purpose I/O 21 (I/O/Z); alternates are eQEP1 input B (input), McBSP-A receive serial data (input), and eCAN-B receive (input). |
| 66 | GPIO22/EQEP1S/MCLKXA/SCITXDB | bidirectional | General-purpose I/O 22 (I/O/Z); alternates are eQEP1 strobe (I/O), McBSP-A transmit clock (I/O), and SCI-B transmit (output). |
| 67 | GPIO23/EQEP1I/MFSXA/SCIRXDB | bidirectional | General-purpose I/O 23 (I/O/Z); alternates are eQEP1 index (I/O), McBSP-A transmit frame sync (I/O), and SCI-B receive (input). |
| 68 | GPIO24/ECAP1/EQEP2A/MDXB | bidirectional | General-purpose I/O 24 (I/O/Z); alternates are eCAP1 input/output (I/O), eQEP2 input A (input), and McBSP-B transmit serial data (output). |
| 69 | GPIO25/ECAP2/EQEP2B/MDRB | bidirectional | General-purpose I/O 25 (I/O/Z); alternates are eCAP2 input/output (I/O), eQEP2 input B (input), and McBSP-B receive serial data (input). |
| 70 | VSS | power_in | Digital ground pin (0 V reference). |
| 71 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 72 | GPIO26/ECAP3/EQEP2I/MCLKXB | bidirectional | General-purpose I/O 26 (I/O/Z); alternates are eCAP3 input/output (I/O), eQEP2 index (I/O), and McBSP-B transmit clock (I/O). |
| 73 | GPIO27/ECAP4/EQEP2S/MFSXB | bidirectional | General-purpose I/O 27 (I/O/Z); alternates are eCAP4 input/output (I/O), eQEP2 strobe (I/O), and McBSP-B transmit frame sync (I/O). |
| 74 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 (I/O/Z); alternates are I2C data open-drain bidirectional (I/OD), external ePWM sync pulse input (input), and ADC start-of-conversion A (output). |
| 75 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 (I/O/Z); alternates are I2C clock open-drain bidirectional (I/OD), external ePWM sync pulse output (output), and ADC start-of-conversion B (output). |
| 76 | TDI | input | JTAG test data input with internal pull-up, sampled on the rising edge of TCK. |
| 77 | TDO | tri_state | JTAG scan test data output, shifted out on the falling edge of TCK (8 mA driver, O/Z). |
| 78 | TRST | input | JTAG test reset with internal pull-down; must be held low during normal operation and requires an external pull-down (typically 2.2 kΩ). |
| 79 | TMS | input | JTAG test mode select with internal pull-up, clocked on the rising edge of TCK in the TAP controller. |
| 80 | XRS | bidirectional | Device reset input and watchdog reset output; open-drain output with internal pull-up, driven low for 512 OSCCLK cycles on a watchdog reset. |
| 81 | TEST1 | unconnected | Reserved by TI; must be left unconnected. |
| 82 | TEST2 | unconnected | Reserved by TI; must be left unconnected. |
| 83 | VSS | power_in | Digital ground pin (0 V reference). |
| 84 | VDD3VFL | power_in | 3.3 V flash core supply; must always be connected to 3.3 V (3.135 V to 3.465 V). |
| 85 | EMU0 | bidirectional | Emulator pin 0 (I/O/Z, 8 mA drive, internal pull-up); requires an external pull-up of about 2.2 kΩ to 4.7 kΩ and is also used with EMU1 to latch boundary-scan mode. |
| 86 | EMU1 | bidirectional | Emulator pin 1 (I/O/Z, 8 mA drive, internal pull-up); requires an external pull-up of about 2.2 kΩ to 4.7 kΩ and is also used with EMU0 to latch boundary-scan mode. |
| 87 | TCK | input | JTAG test clock with internal pull-up. |
| 88 | GPIO48/ECAP5/XD31 | bidirectional | General-purpose I/O 48 (I/O/Z); alternates are eCAP5 input/output (I/O) and XINTF data line 31 (I/O/Z). |
| 89 | GPIO49/ECAP6/XD30 | bidirectional | General-purpose I/O 49 (I/O/Z); alternates are eCAP6 input/output (I/O) and XINTF data line 30 (I/O/Z). |
| 90 | GPIO50/EQEP1A/XD29 | bidirectional | General-purpose I/O 50 (I/O/Z); alternates are eQEP1 input A (input) and XINTF data line 29 (I/O/Z). |
| 91 | GPIO51/EQEP1B/XD28 | bidirectional | General-purpose I/O 51 (I/O/Z); alternates are eQEP1 input B (input) and XINTF data line 28 (I/O/Z). |
| 92 | VSS | power_in | Digital ground pin (0 V reference). |
| 93 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 94 | GPIO52/EQEP1S/XD27 | bidirectional | General-purpose I/O 52 (I/O/Z); alternates are eQEP1 strobe (I/O) and XINTF data line 27 (I/O/Z). |
| 95 | GPIO53/EQEP1I/XD26 | bidirectional | General-purpose I/O 53 (I/O/Z); alternates are eQEP1 index (I/O) and XINTF data line 26 (I/O/Z). |
| 96 | GPIO54/SPISIMOA/XD25 | bidirectional | General-purpose I/O 54 (I/O/Z); alternates are SPI-A slave-in/master-out (I/O) and XINTF data line 25 (I/O/Z). |
| 97 | GPIO55/SPISOMIA/XD24 | bidirectional | General-purpose I/O 55 (I/O/Z); alternates are SPI-A slave-out/master-in (I/O) and XINTF data line 24 (I/O/Z). |
| 98 | GPIO56/SPICLKA/XD23 | bidirectional | General-purpose I/O 56 (I/O/Z); alternates are SPI-A clock (I/O) and XINTF data line 23 (I/O/Z). |
| 99 | GPIO57 | bidirectional | General-purpose I/O 57 (I/O/Z); alternates are SPI-A slave transmit enable (I/O) and XINTF data line 22 (I/O/Z). |
| 100 | GPIO58/MCLKRA/XD21 | bidirectional | General-purpose I/O 58 (I/O/Z); alternates are McBSP-A receive clock (I/O) and XINTF data line 21 (I/O/Z). |
| 101 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 102 | X2 | output | Internal oscillator output; a crystal or ceramic resonator connects between X1 and X2, and X2 is left unconnected if unused. |
| 103 | VSS | power_in | Digital ground pin (0 V reference). |
| 104 | X1 | input | Internal/external oscillator input; accepts a crystal/resonator or a 1.8 V external oscillator (X1 must be tied to GND when a 3.3 V oscillator drives XCLKIN). |
| 105 | XCLKIN | input | External 3.3 V oscillator clock input (4 MHz to 100 MHz for this device); must be tied to GND when a crystal or 1.8 V oscillator on X1 is used. |
| 106 | VSS | power_in | Digital ground pin (0 V reference). |
| 107 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 108 | VSS | power_in | Digital ground pin (0 V reference). |
| 109 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 110 | GPIO59/MFSRA/XD20 | bidirectional | General-purpose I/O 59 (I/O/Z); alternates are McBSP-A receive frame sync (I/O) and XINTF data line 20 (I/O/Z). |
| 111 | GPIO60/MCLKRB/XD19 | bidirectional | General-purpose I/O 60 (I/O/Z); alternates are McBSP-B receive clock (I/O) and XINTF data line 19 (I/O/Z). |
| 112 | GPIO61/MFSRB/XD18 | bidirectional | General-purpose I/O 61 (I/O/Z); alternates are McBSP-B receive frame sync (I/O) and XINTF data line 18 (I/O/Z). |
| 113 | GPIO62/SCIRXDC/XD17 | bidirectional | General-purpose I/O 62 (I/O/Z); alternates are SCI-C receive data (input) and XINTF data line 17 (I/O/Z). |
| 114 | GPIO63/SCITXDC/XD16 | bidirectional | General-purpose I/O 63 (I/O/Z); alternates are SCI-C transmit data (output) and XINTF data line 16 (I/O/Z). |
| 115 | GPIO64/XD15 | bidirectional | General-purpose I/O 64 (I/O/Z); alternate is XINTF data line 15 (I/O/Z). |
| 116 | GPIO65/XD14 | bidirectional | General-purpose I/O 65 (I/O/Z); alternate is XINTF data line 14 (I/O/Z). |
| 117 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 118 | VSS | power_in | Digital ground pin (0 V reference). |
| 119 | GPIO66/XD13 | bidirectional | General-purpose I/O 66 (I/O/Z); alternate is XINTF data line 13 (I/O/Z). |
| 120 | VSS | power_in | Digital ground pin (0 V reference). |
| 121 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 122 | GPIO67/XD12 | bidirectional | General-purpose I/O 67 (I/O/Z); alternate is XINTF data line 12 (I/O/Z). |
| 123 | GPIO68/XD11 | bidirectional | General-purpose I/O 68 (I/O/Z); alternate is XINTF data line 11 (I/O/Z). |
| 124 | GPIO69/XD10 | bidirectional | General-purpose I/O 69 (I/O/Z); alternate is XINTF data line 10 (I/O/Z). |
| 125 | VSS | power_in | Digital ground pin (0 V reference). |
| 126 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 127 | GPIO70/XD9 | bidirectional | General-purpose I/O 70 (I/O/Z); alternate is XINTF data line 9 (I/O/Z). |
| 128 | GPIO71/XD8 | bidirectional | General-purpose I/O 71 (I/O/Z); alternate is XINTF data line 8 (I/O/Z). |
| 129 | GPIO72/XD7 | bidirectional | General-purpose I/O 72 (I/O/Z); alternate is XINTF data line 7 (I/O/Z). |
| 130 | GPIO73/XD6 | bidirectional | General-purpose I/O 73 (I/O/Z); alternate is XINTF data line 6 (I/O/Z). |
| 131 | GPIO74/XD5 | bidirectional | General-purpose I/O 74 (I/O/Z); alternate is XINTF data line 5 (I/O/Z). |
| 132 | GPIO75/XD4 | bidirectional | General-purpose I/O 75 (I/O/Z); alternate is XINTF data line 4 (I/O/Z). |
| 133 | GPIO76/XD3 | bidirectional | General-purpose I/O 76 (I/O/Z); alternate is XINTF data line 3 (I/O/Z). |
| 134 | GPIO77/XD2 | bidirectional | General-purpose I/O 77 (I/O/Z); alternate is XINTF data line 2 (I/O/Z). |
| 135 | GPIO78/XD1 | bidirectional | General-purpose I/O 78 (I/O/Z); alternate is XINTF data line 1 (I/O/Z). |
| 136 | GPIO79/XD0 | bidirectional | General-purpose I/O 79 (I/O/Z); alternate is XINTF data line 0 (I/O/Z). |
| 137 | GPIO38/XWE0 | bidirectional | General-purpose I/O 38 (I/O/Z); alternate is XINTF write enable 0 (output). |
| 138 | XCLKOUT | tri_state | Output clock derived from SYSCLKOUT (equal to, half, or quarter of SYSCLKOUT; reset value SYSCLKOUT/4); it is not placed in high impedance at reset, and can be disabled via XINTCNF2[CLKOFF]. |
| 139 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 140 | VSS | power_in | Digital ground pin (0 V reference). |
| 141 | GPIO28/SCIRXDA/XZCS6 | bidirectional | General-purpose I/O 28 (I/O/Z); alternates are SCI-A receive data (input) and XINTF zone 6 chip select (output). |
| 142 | GPIO34/ECAP1/XREADY | bidirectional | General-purpose I/O 34 (I/O/Z); alternates are eCAP1 input/output (I/O) and XINTF external ready signal (input), which is connected directly to XINTF. |
| 143 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 144 | VSS | power_in | Digital ground pin (0 V reference). |
| 145 | GPIO36/SCIRXDA/XZCS0 | bidirectional | General-purpose I/O 36 (I/O/Z); alternates are SCI-A receive data (input) and XINTF zone 0 chip select (output). |
| 146 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 147 | VSS | power_in | Digital ground pin (0 V reference). |
| 148 | GPIO35/SCITXDA/XR/W | bidirectional | General-purpose I/O 35 (I/O/Z); alternates are SCI-A transmit data (output) and XINTF read, not write, strobe (XR/W, output). |
| 149 | XRD | output | External interface read enable output. |
| 150 | GPIO37/ECAP2/XZCS7 | bidirectional | General-purpose I/O 37 (I/O/Z); alternates are eCAP2 input/output (I/O) and XINTF zone 7 chip select (output). |
| 151 | GPIO40/XA0/XWE1 | bidirectional | General-purpose I/O 40 (I/O/Z); alternates are XINTF address line 0 / XINTF write enable 1 (output). |
| 152 | GPIO41/XA1 | bidirectional | General-purpose I/O 41 (I/O/Z); alternate is XINTF address line 1 (output). |
| 153 | GPIO42/XA2 | bidirectional | General-purpose I/O 42 (I/O/Z); alternate is XINTF address line 2 (output). |
| 154 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 155 | VSS | power_in | Digital ground pin (0 V reference). |
| 156 | GPIO43/XA3 | bidirectional | General-purpose I/O 43 (I/O/Z); alternate is XINTF address line 3 (output). |
| 157 | GPIO44/XA4 | bidirectional | General-purpose I/O 44 (I/O/Z); alternate is XINTF address line 4 (output). |
| 158 | GPIO45/XA5 | bidirectional | General-purpose I/O 45 (I/O/Z); alternate is XINTF address line 5 (output). |
| 159 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 160 | VSS | power_in | Digital ground pin (0 V reference). |
| 161 | GPIO46/XA6 | bidirectional | General-purpose I/O 46 (I/O/Z); alternate is XINTF address line 6 (output). |
| 162 | GPIO47/XA7 | bidirectional | General-purpose I/O 47 (I/O/Z); alternate is XINTF address line 7 (output). |
| 163 | GPIO80/XA8 | bidirectional | General-purpose I/O 80 (I/O/Z); alternate is XINTF address line 8 (output). |
| 164 | GPIO81/XA9 | bidirectional | General-purpose I/O 81 (I/O/Z); alternate is XINTF address line 9 (output). |
| 165 | GPIO82/XA10 | bidirectional | General-purpose I/O 82 (I/O/Z); alternate is XINTF address line 10 (output). |
| 166 | VSS | power_in | Digital ground pin (0 V reference). |
| 167 | VDD | power_in | CPU and logic digital core supply; 1.71 V to 1.89 V (1.8 V nominal) for the 100 MHz device. |
| 168 | GPIO83/XA11 | bidirectional | General-purpose I/O 83 (I/O/Z); alternate is XINTF address line 11 (output). |
| 169 | GPIO84/XA12 | bidirectional | General-purpose I/O 84 (I/O/Z); alternate is XINTF address line 12 (output). |
| 170 | VDDIO | power_in | Digital I/O supply; 3.135 V to 3.465 V (3.3 V nominal). |
| 171 | VSS | power_in | Digital ground pin (0 V reference). |
| 172 | GPIO85/XA13 | bidirectional | General-purpose I/O 85 (I/O/Z); alternate is XINTF address line 13 (output). |
| 173 | GPIO86/XA14 | bidirectional | General-purpose I/O 86 (I/O/Z); alternate is XINTF address line 14 (output). |
| 174 | GPIO87/XA15 | bidirectional | General-purpose I/O 87 (I/O/Z); alternate is XINTF address line 15 (output). |
| 175 | GPIO39/XA16 | bidirectional | General-purpose I/O 39 (I/O/Z); alternate is XINTF address line 16 (output). |
| 176 | GPIO31/CANTXA/XA17 | bidirectional | General-purpose I/O 31 (I/O/Z); alternates are eCAN-A transmit (output) and XINTF address line 17 (output). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-176(24x24) |
| Category | Embedded Processors & Controllers |
| Pins | 176 |
CAD (KiCad official)
- Symbol:
TMS320F28333PGFA - Footprint:
Package_QFP:LQFP-176_24x24mm_P0.5mm - 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
- 3D model files:
tms320f28333pgfa-etched.step/tms320f28333pgfa-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28333pgfa.step/tms320f28333pgfa.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (218 pp, sha256
5a21b6765ede7b5a, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).