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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS320F2812PGFQ

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-176(24x24)

TMS320F2812PGFQ from Texas Instruments, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDAIO	power_in	3.3-V analog I/O power pin.
2	ADCINB0	input	ADC analog input 0 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
3	ADCINB1	input	ADC analog input 1 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
4	ADCINB2	input	ADC analog input 2 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
5	ADCINB3	input	ADC analog input 3 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
6	ADCINB4	input	ADC analog input 4 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
7	ADCINB5	input	ADC analog input 5 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
8	ADCINB6	input	ADC analog input 6 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
9	ADCINB7	input	ADC analog input 7 for Sample-and-Hold B; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
10	ADCREFM	bidirectional	ADC 1-V reference output requiring a low-ESR (under 1.5 ohm) 10 uF ceramic capacitor to analog ground, or an external 1-V reference input when enabled in software.
11	ADCREFP	bidirectional	ADC 2-V reference output requiring a low-ESR (under 1.5 ohm) 10 uF ceramic capacitor to analog ground, or an external 2-V reference input when enabled in software.
12	AVSSREFBG	power_in	ADC analog ground.
13	AVDDREFBG	power_in	ADC analog power (3.3 V).
14	VDDA1	power_in	ADC analog 3.3-V supply.
15	VSSA1	power_in	ADC analog ground.
16	ADCRESEXT	output	ADC external current bias resistor: 24.9 kohm ±5% for ADC clock 1-18.75 MHz, 20 kohm ±5% for 18.75-25 MHz.
17	XMP/MC	input	Microprocessor/microcomputer mode select with internal pulldown; high enables Zone 7 on the external interface, low enables on-chip boot ROM.
18	XA[0]	tri_state	XINTF 19-bit address bus bit 0 (output/high-impedance).
19	VSS	power_in	Core and digital I/O ground pin.
20	GPIOF13 - MDRA	bidirectional	GPIO or McBSP received serial data input, with internal pullup.
21	XD[0]	tri_state	XINTF 16-bit data bus bit 0 (I/O/Z) with internal pullup.
22	GPIOF12 - MDXA	bidirectional	GPIO or McBSP transmitted serial data output.
23	VDD	power_in	1.8-V or 1.9-V core digital power pin.
24	XD[1]	tri_state	XINTF 16-bit data bus bit 1 (I/O/Z) with internal pullup.
25	GPIOF9 - MCLKRA	bidirectional	GPIO or McBSP receive clock, with internal pullup.
26	GPIOF10 - MFSXA	bidirectional	GPIO or McBSP transmit frame synch, with internal pullup.
27	XD[2]	tri_state	XINTF 16-bit data bus bit 2 (I/O/Z) with internal pullup.
28	GPIOF8 - MCLKXA	bidirectional	GPIO or McBSP transmit clock, with internal pullup.
29	GPIOF11 - MFSRA	bidirectional	GPIO or McBSP receive frame synch, with internal pullup.
30	XD[3]	tri_state	XINTF 16-bit data bus bit 3 (I/O/Z) with internal pullup.
31	VDDIO	power_in	3.3-V I/O digital power pin.
32	VSS	power_in	Core and digital I/O ground pin.
33	XD[4]	tri_state	XINTF 16-bit data bus bit 4 (I/O/Z) with internal pullup.
34	GPIOF2 - SPICLKA	bidirectional	GPIO or SPI clock.
35	GPIOF3 - SPISTEA	bidirectional	GPIO or SPI slave transmit enable.
36	XD[5]	tri_state	XINTF 16-bit data bus bit 5 (I/O/Z) with internal pullup.
37	VDD	power_in	1.8-V or 1.9-V core digital power pin.
38	VSS	power_in	Core and digital I/O ground pin.
39	XD[6]	tri_state	XINTF 16-bit data bus bit 6 (I/O/Z) with internal pullup.
40	GPIOF0 - SPISIMOA	bidirectional	GPIO or SPI slave in, master out.
41	GPIOF1 - SPISOMIA	bidirectional	GPIO or SPI slave out, master in.
42	XRD	tri_state	Active-low XINTF read strobe, mutually exclusive with XWE.
43	XA[1]	tri_state	XINTF 19-bit address bus bit 1 (output/high-impedance).
44	XZCS0AND1	tri_state	XINTF Zone 0 and Zone 1 chip select, active low.
45	GPIOB0 - PWM7	bidirectional	GPIO or PWM output pin #7, with internal pullup.
46	GPIOB1 - PWM8	bidirectional	GPIO or PWM output pin #8, with internal pullup.
47	GPIOB2 - PWM9	bidirectional	GPIO or PWM output pin #9, with internal pullup.
48	GPIOB3 - PWM10	bidirectional	GPIO or PWM output pin #10, with internal pullup.
49	GPIOB4 - PWM11	bidirectional	GPIO or PWM output pin #11, with internal pullup.
50	GPIOB5 - PWM12	bidirectional	GPIO or PWM output pin #12, with internal pullup.
51	XR/W	tri_state	Read-not-write strobe, normally held high; low indicates a write cycle, high a read cycle.
52	VSS	power_in	Core and digital I/O ground pin.
53	GPIOB6 - T3PWM_T3CMP	bidirectional	GPIO or Timer 3 output, with internal pullup.
54	XD[7]	tri_state	XINTF 16-bit data bus bit 7 (I/O/Z) with internal pullup.
55	GPIOB7 - T4PWM_T4CMP	bidirectional	GPIO or Timer 4 output, with internal pullup.
56	VDD	power_in	1.8-V or 1.9-V core digital power pin.
57	GPIOB8 - CAP4_QEP3	bidirectional	GPIO or capture input #4, with internal pullup.
58	VSS	power_in	Core and digital I/O ground pin.
59	GPIOB9 - CAP5_QEP4	bidirectional	GPIO or capture input #5, with internal pullup.
60	GPIOB10 - CAP6_QEPI2	bidirectional	GPIO or capture input #6, with internal pullup.
61	GPIOB13 - C4TRIP	bidirectional	GPIO or Compare 4 output trip, with internal pullup.
62	GPIOB14 - C5TRIP	bidirectional	GPIO or Compare 5 output trip, with internal pullup.
63	GPIOB15 - C6TRIP	bidirectional	GPIO or Compare 6 output trip, with internal pullup.
64	VDDIO	power_in	3.3-V I/O digital power pin.
65	XD[8]	tri_state	XINTF 16-bit data bus bit 8 (I/O/Z) with internal pullup.
66	TEST2	bidirectional	Test pin reserved for TI; must be left unconnected on F281x devices.
67	TEST1	bidirectional	Test pin reserved for TI; must be left unconnected on F281x devices.
68	XD[9]	tri_state	XINTF 16-bit data bus bit 9 (I/O/Z) with internal pullup.
69	VDD3VFL	power_in	3.3-V flash core power pin, to be connected to 3.3 V at all times after power-up sequence requirements are met.
70	VSS	power_in	Core and digital I/O ground pin.
71	GPIOB11 - TDIRB	bidirectional	GPIO or timer direction input, with internal pullup.
72	GPIOB12 - TCLKINB	bidirectional	GPIO or timer clock input, with internal pullup.
73	XD[10]	tri_state	XINTF 16-bit data bus bit 10 (I/O/Z) with internal pullup.
74	XD[11]	tri_state	XINTF 16-bit data bus bit 11 (I/O/Z) with internal pullup.
75	VDD	power_in	1.8-V or 1.9-V core digital power pin.
76	X2	output	Oscillator output.
77	X1/XCLKIN	input	Oscillator input or external clock input, referenced to the 1.8-V (or 1.9-V) core supply VDD rather than VDDIO.
78	VSS	power_in	Core and digital I/O ground pin.
79	GPIOD5 - T3CTRIP_PDPINTB	bidirectional	GPIO or Timer 3 compare output trip, with internal pullup.
80	XA[2]	tri_state	XINTF 19-bit address bus bit 2 (output/high-impedance).
81	VDDIO	power_in	3.3-V I/O digital power pin.
82	XHOLDA	tri_state	External hold acknowledge, driven active low when the XINTF has granted an XHOLD request and all buses and strobes are high-impedance.
83	GPIOD6 - T4CTRIP/EVBSOC	bidirectional	GPIO or Timer 4 compare output trip or external ADC start-of-conversion EV-B, with internal pullup.
84	XWE	tri_state	Active-low XINTF write strobe with waveform set per zone by XTIMINGx registers.
85	XA[3]	tri_state	XINTF 19-bit address bus bit 3 (output/high-impedance).
86	VSS	power_in	Core and digital I/O ground pin.
87	GPIOF6 - CANTXA	bidirectional	GPIO or eCAN transmit data, with internal pullup.
88	XZCS2	tri_state	XINTF Zone 2 chip select, active low.
89	GPIOF7 - CANRXA	bidirectional	GPIO or eCAN receive data, with internal pullup.
90	GPIOG4 - SCITXDB	bidirectional	GPIO or SCI-B asynchronous serial port transmit data.
91	GPIOG5 - SCIRXDB	bidirectional	GPIO or SCI-B asynchronous serial port receive data.
92	GPIOA0 - PWM1	bidirectional	GPIO or PWM output pin #1, with internal pullup.
93	GPIOA1 - PWM2	bidirectional	GPIO or PWM output pin #2, with internal pullup.
94	GPIOA2 - PWM3	bidirectional	GPIO or PWM output pin #3, with internal pullup.
95	GPIOA3 - PWM4	bidirectional	GPIO or PWM output pin #4, with internal pullup.
96	XD[12]	tri_state	XINTF 16-bit data bus bit 12 (I/O/Z) with internal pullup.
97	XD[13]	tri_state	XINTF 16-bit data bus bit 13 (I/O/Z) with internal pullup.
98	GPIOA4 - PWM5	bidirectional	GPIO or PWM output pin #5, with internal pullup.
99	VSS	power_in	Core and digital I/O ground pin.
100	VDD	power_in	1.8-V or 1.9-V core digital power pin.
101	GPIOA5 - PWM6	bidirectional	GPIO or PWM output pin #6, with internal pullup.
102	GPIOA6 - T1PWM_T1CMP	bidirectional	GPIO or Timer 1 output, with internal pullup.
103	XA[4]	tri_state	XINTF 19-bit address bus bit 4 (output/high-impedance).
104	GPIOA7 - T2PWM_T2CMP	bidirectional	GPIO or Timer 2 output, with internal pullup.
105	VSS	power_in	Core and digital I/O ground pin.
106	GPIOA8 - CAP1_QEP1	bidirectional	GPIO or capture input #1, with internal pullup.
107	GPIOA9 - CAP2_QEP2	bidirectional	GPIO or capture input #2, with internal pullup.
108	XA[5]	tri_state	XINTF 19-bit address bus bit 5 (output/high-impedance).
109	GPIOA10 - CAP3_QEPI1	bidirectional	GPIO or capture input #3, with internal pullup.
110	GPIOD0 - T1CTRIP_PDPINTA	bidirectional	GPIO or Timer 1 compare output trip, with internal pullup.
111	XA[6]	tri_state	XINTF 19-bit address bus bit 6 (output/high-impedance).
112	VDD	power_in	1.8-V or 1.9-V core digital power pin.
113	VSS	power_in	Core and digital I/O ground pin.
114	VDDIO	power_in	3.3-V I/O digital power pin.
115	GPIOD1 - T2CTRIP/EVASOC	bidirectional	GPIO or Timer 2 compare output trip or external ADC start-of-conversion EV-A, with internal pullup.
116	GPIOA11 - TDIRA	bidirectional	GPIO or timer direction input, with internal pullup.
117	GPIOA12 - TCLKINA	bidirectional	GPIO or timer clock input, with internal pullup.
118	XA[7]	tri_state	XINTF 19-bit address bus bit 7 (output/high-impedance).
119	XCLKOUT	output	Output clock derived from SYSCLKOUT at the same, 1/2 or 1/4 frequency (1/4 at reset); not high-impedance during reset and can be turned off via CLKOFF in XINTCNF2.
120	VSS	power_in	Core and digital I/O ground pin.
121	XA[8]	tri_state	XINTF 19-bit address bus bit 8 (output/high-impedance).
122	GPIOA13 - C1TRIP	bidirectional	GPIO or Compare 1 output trip, with internal pullup.
123	GPIOA14 - C2TRIP	bidirectional	GPIO or Compare 2 output trip, with internal pullup.
124	GPIOA15 - C3TRIP	bidirectional	GPIO or Compare 3 output trip, with internal pullup.
125	XA[9]	tri_state	XINTF 19-bit address bus bit 9 (output/high-impedance).
126	TMS	input	JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK.
127	TDO	tri_state	JTAG test data output, shifted out on the falling edge of TCK.
128	VDD	power_in	1.8-V or 1.9-V core digital power pin.
129	VSS	power_in	Core and digital I/O ground pin.
130	XA[10]	tri_state	XINTF 19-bit address bus bit 10 (output/high-impedance).
131	TDI	input	JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK.
132	XA[11]	tri_state	XINTF 19-bit address bus bit 11 (output/high-impedance).
133	XZCS6AND7	tri_state	XINTF Zone 6 and Zone 7 chip select, active low.
134	TESTSEL	input	Test pin reserved for TI with internal pulldown; must be connected to ground.
135	TRST	input	Active-high JTAG test reset with internal pulldown; must be kept low during normal operation and should not use a pullup resistor.
136	TCK	input	JTAG test clock with internal pullup.
137	EMU0	tri_state	Emulator pin 0 with internal pullup; an external 2.2-kohm to 4.7-kohm pullup is recommended.
138	XA[12]	tri_state	XINTF 19-bit address bus bit 12 (output/high-impedance).
139	XD[14]	tri_state	XINTF 16-bit data bus bit 14 (I/O/Z) with internal pullup.
140	GPIOF14 - XF_XPLLDIS	bidirectional	GPIO, XF general-purpose output, or XPLLDIS sampled during reset (PLL disabled if sensed low), with internal pullup.
141	XA[13]	tri_state	XINTF 19-bit address bus bit 13 (output/high-impedance).
142	VSS	power_in	Core and digital I/O ground pin.
143	VDD	power_in	1.8-V or 1.9-V core digital power pin.
144	XA[14]	tri_state	XINTF 19-bit address bus bit 14 (output/high-impedance).
145	VDDIO	power_in	3.3-V I/O digital power pin.
146	EMU1	tri_state	Emulator pin 1 with internal pullup; an external 2.2-kohm to 4.7-kohm pullup is recommended.
147	XD[15]	tri_state	XINTF 16-bit data bus bit 15 (I/O/Z) with internal pullup.
148	XA[15]	tri_state	XINTF 19-bit address bus bit 15 (output/high-impedance).
149	GPIOE0 - XINT1_XBIO	tri_state	GPIO or XINT1 or XBIO input.
150	GPIOE2 - XNMI_XINT13	bidirectional	GPIO or XNMI or XINT13, with internal pullup.
151	GPIOE1 - XINT2_ADCSOC	tri_state	GPIO or XINT2 or ADC start-of-conversion.
152	XA[16]	tri_state	XINTF 19-bit address bus bit 16 (output/high-impedance).
153	VSS	power_in	Core and digital I/O ground pin.
154	VDD	power_in	1.8-V or 1.9-V core digital power pin.
155	GPIOF4 - SCITXDA	bidirectional	GPIO or SCI-A asynchronous serial port TX data, with internal pullup.
156	XA[17]	tri_state	XINTF 19-bit address bus bit 17 (output/high-impedance).
157	GPIOF5 - SCIRXDA	bidirectional	GPIO or SCI-A asynchronous serial port RX data, with internal pullup.
158	XA[18]	tri_state	XINTF 19-bit address bus bit 18 (output/high-impedance).
159	XHOLD	input	External hold request with internal pullup; when low it requests the XINTF to release the external bus and place buses and strobes in high impedance.
160	XRS	bidirectional	Device reset input and watchdog reset output, open-drain with internal pullup (100 uA typical); execution restarts at the address at 0x3FFFC0 when released high.
161	XREADY	input	XINTF ready input with internal pullup, indicating the peripheral is ready to complete the access when asserted to 1.
162	VDD1	power_in	ADC digital 1.8-V (or 1.9-V) supply.
163	VSS1	power_in	ADC digital ground.
164	ADCBGREFIN	passive	Test pin reserved for TI; must be left unconnected.
165	VSSA2	power_in	ADC analog ground.
166	VDDA2	power_in	ADC analog 3.3-V supply.
167	ADCINA7	input	ADC analog input 7 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
168	ADCINA6	input	ADC analog input 6 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
169	ADCINA5	input	ADC analog input 5 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
170	ADCINA4	input	ADC analog input 4 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
171	ADCINA3	input	ADC analog input 3 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
172	ADCINA2	input	ADC analog input 2 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
173	ADCINA1	input	ADC analog input 1 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
174	ADCINA0	input	ADC analog input 0 for Sample-and-Hold A; should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered.
175	ADCLO	passive	Common low-side analog input; connect to analog ground.
176	VSSAIO	power_in	Analog I/O ground pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-176(24x24)
Category	Embedded Processors & Controllers
Pins	176

CAD (KiCad official)

Symbol: TMS320F2812PGFQ
Footprint: Package_QFP:LQFP-176_24x24mm_P0.5mm
3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
3D model files: tms320f2812pgfq-etched.step / tms320f2812pgfq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2812pgfq.step / tms320f2812pgfq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (173 pp, sha256 3c891c6ecdaa247f, retrieved 2026-10-06, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF