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TMS320F2811PBKS

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS320F2811PBKS

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-128(14x14)

TMS320F2811PBKS from Texas Instruments, in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDAIO power_in 3.3-V analog I/O power pin.
2 ADCINB0 input Analog input channel B0 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
3 ADCINB1 input Analog input channel B1 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
4 ADCINB2 input Analog input channel B2 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
5 ADCINB3 input Analog input channel B3 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
6 ADCINB4 input Analog input channel B4 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
7 ADCINB5 input Analog input channel B5 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
8 ADCINB6 input Analog input channel B6 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
9 ADCINB7 input Analog input channel B7 for Sample-and-Hold B; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
10 ADCREFM bidirectional ADC 1-V reference output requiring a low-ESR (under 1.5 Ω) 10 µF ceramic bypass to analog ground; it can accept a 1-V external reference when the software bit is enabled.
11 ADCREFP bidirectional ADC 2-V reference output requiring a low-ESR (under 1.5 Ω) 10 µF ceramic bypass to analog ground; it can accept a 2-V external reference when the software bit is enabled.
12 AVSSREFBG power_in ADC analog ground.
13 AVDDREFBG power_in ADC analog power, 3.3 V.
14 VDDA1 power_in ADC analog 3.3-V supply.
15 VSSA1 power_in ADC analog ground.
16 ADCRESEXT output ADC external current bias resistor: use 24.9 kΩ ±5% for ADC clock 1-18.75 MHz, or 20 kΩ ±5% for 18.75-25 MHz.
17 VSS power_in Core and digital I/O ground pin.
18 GPIOF13/MDRA bidirectional GPIO or McBSP-A received serial data input; internal pullup.
19 GPIOF12/MDXA bidirectional GPIO or McBSP-A transmitted serial data output; no internal pullup.
20 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
21 GPIOF9/MCLKRA bidirectional GPIO or McBSP receive clock; internal pullup.
22 GPIOF10/MFSXA bidirectional GPIO or McBSP transmit frame synchronization; internal pullup.
23 GPIOF8/MCLKXA bidirectional GPIO or McBSP transmit clock; internal pullup.
24 GPIOF11/MFSRA bidirectional GPIO or McBSP receive frame synchronization; internal pullup.
25 VDDIO power_in 3.3-V I/O digital power pin.
26 VSS power_in Core and digital I/O ground pin.
27 GPIOF2/SPICLKA bidirectional GPIO or SPI clock; no internal pullup.
28 GPIOF3/SPISTEA bidirectional GPIO or SPI slave transmit enable; no internal pullup.
29 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
30 VSS power_in Core and digital I/O ground pin.
31 GPIOF0/SPISIMOA bidirectional GPIO or SPI slave-in/master-out; no internal pullup.
32 GPIOF1/SPISOMIA bidirectional GPIO or SPI slave-out/master-in; no internal pullup.
33 GPIOB0/PWM7 bidirectional GPIO or PWM output pin 7; internal pullup.
34 GPIOB1/PWM8 bidirectional GPIO or PWM output pin 8; internal pullup.
35 GPIOB2/PWM9 bidirectional GPIO or PWM output pin 9; internal pullup.
36 GPIOB3/PWM10 bidirectional GPIO or PWM output pin 10; internal pullup.
37 GPIOB4/PWM11 bidirectional GPIO or PWM output pin 11; internal pullup.
38 GPIOB5/PWM12 bidirectional GPIO or PWM output pin 12; internal pullup.
39 VSS power_in Core and digital I/O ground pin.
40 GPIOB6/T3PWM_T3CMP bidirectional GPIO or GP Timer 3 PWM/compare output; internal pullup.
41 GPIOB7/T4PWM_T4CMP bidirectional GPIO or GP Timer 4 PWM/compare output; internal pullup.
42 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
43 GPIOB8/CAP4_QEP3 bidirectional GPIO or capture input 4 (QEP3); internal pullup.
44 GPIOB9/CAP5_QEP4 bidirectional GPIO or capture input 5 (QEP4); internal pullup.
45 GPIOB10/CAP6_QEPI2 bidirectional GPIO or capture input 6 (QEPI2); internal pullup.
46 GPIOB13/C4TRIP bidirectional GPIO or compare 4 output trip input; internal pullup.
47 GPIOB14/C5TRIP bidirectional GPIO or compare 5 output trip input; internal pullup.
48 GPIOB15/C6TRIP bidirectional GPIO or compare 6 output trip input; internal pullup.
49 VDDIO power_in 3.3-V I/O digital power pin.
50 TEST2 bidirectional Test pin reserved for TI; must be left unconnected on F281x devices.
51 TEST1 bidirectional Test pin reserved for TI; must be left unconnected on F281x devices.
52 VDD3VFL power_in 3.3-V flash core power pin; connect to 3.3 V at all times after power-up sequence requirements have been met.
53 VSS power_in Core and digital I/O ground pin.
54 GPIOB11/TDIRB bidirectional GPIO or timer direction input B; internal pullup.
55 GPIOB12/TCLKINB bidirectional GPIO or timer clock input B; internal pullup.
56 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
57 X2 output Oscillator output.
58 X1/XCLKIN input Oscillator input or external clock input, referenced to the 1.8-V (or 1.9-V) core supply VDD rather than VDDIO; a clamp diode or a 1.8-V oscillator may be needed.
59 VSS power_in Core and digital I/O ground pin.
60 GPIOD5/T3CTRIP_PDPINTB bidirectional GPIO or timer 3 compare output trip (PDPINTB); internal pullup.
61 GPIOD6/T4CTRIP/EVBSOC bidirectional GPIO or timer 4 compare output trip, or external ADC start-of-conversion EV-B; internal pullup.
62 VSS power_in Core and digital I/O ground pin.
63 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
64 GPIOF6/CANTXA bidirectional GPIO or eCAN transmit data; internal pullup.
65 GPIOF7/CANRXA bidirectional GPIO or eCAN receive data; internal pullup.
66 GPIOG4/SCITXDB bidirectional GPIO or SCI-B asynchronous serial transmit data; no internal pullup.
67 GPIOG5/SCIRXDB bidirectional GPIO or SCI-B asynchronous serial receive data; no internal pullup.
68 GPIOA0/PWM1 bidirectional GPIO or PWM output pin 1; internal pullup.
69 GPIOA1/PWM2 bidirectional GPIO or PWM output pin 2; internal pullup.
70 GPIOA2/PWM3 bidirectional GPIO or PWM output pin 3; internal pullup.
71 GPIOA3/PWM4 bidirectional GPIO or PWM output pin 4; internal pullup.
72 GPIOA4/PWM5 bidirectional GPIO or PWM output pin 5; internal pullup.
73 VSS power_in Core and digital I/O ground pin.
74 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
75 GPIOA5/PWM6 bidirectional GPIO or PWM output pin 6; internal pullup.
76 GPIOA6/T1PWM_T1CMP bidirectional GPIO or timer 1 PWM/compare output; internal pullup.
77 GPIOA7/T2PWM_T2CMP bidirectional GPIO or timer 2 PWM/compare output; internal pullup.
78 GPIOA8/CAP1_QEP1 bidirectional GPIO or capture input 1 (QEP1); internal pullup.
79 GPIOA9/CAP2_QEP2 bidirectional GPIO or capture input 2 (QEP2); internal pullup.
80 GPIOA10/CAP3_QEPI1 bidirectional GPIO or capture input 3 (QEPI1); internal pullup.
81 GPIOD0/T1CTRIP_PDPINTA bidirectional GPIO or timer 1 compare output trip (PDPINTA in 24x/240x-compatible mode); internal pullup.
82 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
83 VDDIO power_in 3.3-V I/O digital power pin.
84 GPIOD1/T2CTRIP/EVASOC bidirectional GPIO or timer 2 compare output trip, or external ADC start-of-conversion EV-A; internal pullup.
85 GPIOA11/TDIRA bidirectional GPIO or timer direction input A; internal pullup.
86 GPIOA12/TCLKINA bidirectional GPIO or timer clock input A; internal pullup.
87 XCLKOUT output Output clock derived from SYSCLKOUT at the same, 1/2 or 1/4 frequency (SYSCLKOUT/4 at reset); not placed in high impedance during reset.
88 VSS power_in Core and digital I/O ground pin.
89 GPIOA13/C1TRIP bidirectional GPIO or compare 1 output trip input; internal pullup.
90 GPIOA14/C2TRIP bidirectional GPIO or compare 2 output trip input; internal pullup.
91 GPIOA15/C3TRIP bidirectional GPIO or compare 3 output trip input; internal pullup.
92 TMS input JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK.
93 TDO tri_state JTAG scan-out test data output, shifted out on the falling edge of TCK; typical drive strength 8 mA.
94 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
95 VSS power_in Core and digital I/O ground pin.
96 TDI input JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK.
97 TESTSEL input Test pin reserved for TI; must be connected to ground (internal pulldown).
98 TRST input JTAG test reset with internal pulldown; must not use a pullup and must be held low during normal operation.
99 TCK input JTAG test clock with internal pullup.
100 EMU0 bidirectional Emulator pin 0 with internal pullup; an external 2.2-kΩ to 4.7-kΩ pullup is recommended, and with EMU1 low a rising edge on TRST latches boundary-scan mode.
101 GPIOF14/XF_XPLLDIS bidirectional General-purpose XF output; sampled during reset, where a low level disables the PLL so HALT and STANDBY modes cannot be used; also a GPIO.
102 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
103 VSS power_in Core and digital I/O ground pin.
104 VDDIO power_in 3.3-V I/O digital power pin.
105 EMU1 bidirectional Emulator pin 1 with internal pullup; an external 2.2-kΩ to 4.7-kΩ pullup is recommended, and it is used with EMU0 to enter boundary-scan mode.
106 GPIOE0/XINT1_XBIO bidirectional GPIO or XINT1 or XBIO input; no internal pullup.
107 GPIOE2/XNMI_XINT13 bidirectional GPIO or XNMI or XINT13 input; internal pullup.
108 GPIOE1/XINT2_ADCSOC bidirectional GPIO or XINT2 or ADC start-of-conversion input; no internal pullup.
109 VSS power_in Core and digital I/O ground pin.
110 VDD power_in 1.8-V or 1.9-V core digital power pin; see Section 5.4 for voltage requirements.
111 GPIOF4/SCITXDA bidirectional GPIO or SCI-A asynchronous serial transmit data; internal pullup.
112 GPIOF5/SCIRXDA bidirectional GPIO or SCI-A asynchronous serial receive data; internal pullup.
113 XRS bidirectional Device reset input and watchdog reset output; open-drain with 100-µA typical internal pullup, driven low for 512 XCLKIN cycles during watchdog reset.
114 VDD1 power_in ADC digital 1.8-V (or 1.9-V) supply.
115 VSS1 power_in ADC digital ground.
116 ADCBGREFIN unconnected Test pin reserved for TI; must be left unconnected.
117 VSSA2 power_in ADC analog ground.
118 VDDA2 power_in ADC analog 3.3-V supply.
119 ADCINA7 input Analog input channel A7 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
120 ADCINA6 input Analog input channel A6 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
121 ADCINA5 input Analog input channel A5 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
122 ADCINA4 input Analog input channel A4 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
123 ADCINA3 input Analog input channel A3 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
124 ADCINA2 input Analog input channel A2 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
125 ADCINA1 input Analog input channel A1 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
126 ADCINA0 input Analog input channel A0 for Sample-and-Hold A; the ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
127 ADCLO passive Common low-side analog input; connect to analog ground.
128 VSSAIO power_in Analog I/O ground pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-128(14x14)
Category Embedded Processors & Controllers
Pins 128

CAD (KiCad official)

  • Symbol: TMS320F2811PBKS
  • Footprint: Package_QFP:LQFP-128_14x14mm_P0.4mm
  • 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2811pbks-etched.step / tms320f2811pbks-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2811pbks.step / tms320f2811pbks.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (173 pp, sha256 3c891c6ecdaa247f, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF