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tms320f2810pbka

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F2810PBKA

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-128(14x14)

TMS320F2810PBKA from Texas Instruments, in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDAIO power_in 3.3-V analog I/O power pin.
2 ADCINB0 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
3 ADCINB1 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
4 ADCINB2 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
5 ADCINB3 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
6 ADCINB4 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
7 ADCINB5 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
8 ADCINB6 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
9 ADCINB7 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold B; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
10 ADCREFM bidirectional ADC voltage reference output (1 V) requiring a low-ESR (under 1.5 ohm) 10 uF ceramic bypass capacitor to analog ground; can accept an external 1 V reference.
11 ADCREFP bidirectional ADC voltage reference output (2 V) requiring a low-ESR (under 1.5 ohm) 10 uF ceramic bypass capacitor to analog ground; can accept an external 2 V reference.
12 AVSSREFBG power_in ADC analog ground.
13 AVDDREFBG power_in ADC analog power, 3.3 V.
14 VDDA1 power_in ADC analog 3.3-V supply.
15 VSSA1 power_in ADC analog ground.
16 ADCRESEXT output ADC external current bias resistor: use 24.9 kohm ±5% for ADC clock range 1-18.75 MHz; use 20 kohm ±5% for ADC clock range 18.75-25 MHz.
17 VSS power_in Core and digital I/O ground pin.
18 GPIOF13/MDRA bidirectional GPIO or McBSP received serial data.
19 GPIOF12/MDXA bidirectional GPIO or McBSP transmitted serial data.
20 VDD power_in 1.8-V or 1.9-V core digital power pin.
21 GPIOF9/MCLKRA bidirectional GPIO or McBSP receive clock.
22 GPIOF10/MFSXA bidirectional GPIO or McBSP transmit frame sync.
23 GPIOF8/MCLKXA bidirectional GPIO or McBSP transmit clock.
24 GPIOF11/MFSRA bidirectional GPIO or McBSP receive frame sync.
25 VDDIO power_in 3.3-V I/O digital power pin.
26 VSS power_in Core and digital I/O ground pin.
27 GPIOF2/SPICLKA bidirectional GPIO or SPI clock.
28 GPIOF3/SPISTEA bidirectional GPIO or SPI slave transmit enable.
29 VDD power_in 1.8-V or 1.9-V core digital power pin.
30 VSS power_in Core and digital I/O ground pin.
31 GPIOF0/SPISIMOA bidirectional GPIO or SPI slave in, master out.
32 GPIOF1/SPISOMIA bidirectional GPIO or SPI slave out, master in.
33 GPIOB0/PWM7 bidirectional GPIO or PWM output pin #7; internal pullup.
34 GPIOB1/PWM8 bidirectional GPIO or PWM output pin #8; internal pullup.
35 GPIOB2/PWM9 bidirectional GPIO or PWM output pin #9; internal pullup.
36 GPIOB3/PWM10 bidirectional GPIO or PWM output pin #10; internal pullup.
37 GPIOB4/PWM11 bidirectional GPIO or PWM output pin #11; internal pullup.
38 GPIOB5/PWM12 bidirectional GPIO or PWM output pin #12; internal pullup.
39 VSS power_in Core and digital I/O ground pin.
40 GPIOB6/T3PWM_T3CMP bidirectional GPIO or timer 3 output.
41 GPIOB7/T4PWM_T4CMP bidirectional GPIO or timer 4 output.
42 VDD power_in 1.8-V or 1.9-V core digital power pin.
43 GPIOB8/CAP4_QEP3 bidirectional GPIO or capture input #4.
44 GPIOB9/CAP5_QEP4 bidirectional GPIO or capture input #5.
45 GPIOB10/CAP6_QEPI2 bidirectional GPIO or capture input #6.
46 GPIOB13/C4TRIP bidirectional GPIO or compare 4 output trip.
47 GPIOB14/C5TRIP bidirectional GPIO or compare 5 output trip.
48 GPIOB15/C6TRIP bidirectional GPIO or compare 6 output trip.
49 VDDIO power_in 3.3-V I/O digital power pin.
50 TEST2 unconnected Test pin reserved for TI; must be left unconnected on F281x devices.
51 TEST1 unconnected Test pin reserved for TI; must be left unconnected on F281x devices.
52 VDD3VFL power_in 3.3-V flash core power pin; should be connected to 3.3 V at all times after power-up sequence requirements are met.
53 VSS power_in Core and digital I/O ground pin.
54 GPIOB11/TDIRB bidirectional GPIO or timer direction input.
55 GPIOB12/TCLKINB bidirectional GPIO or timer clock input.
56 VDD power_in 1.8-V or 1.9-V core digital power pin.
57 X2 output Oscillator output.
58 X1/XCLKIN input Oscillator input to the internal oscillator, also used to feed an external clock referenced to the 1.8-V (or 1.9-V) core supply VDD rather than VDDIO.
59 VSS power_in Core and digital I/O ground pin.
60 GPIOD5/T3CTRIP_PDPINTB bidirectional GPIO or timer 3 compare output trip.
61 GPIOD6/T4CTRIP/EVBSOC bidirectional GPIO or timer 4 compare output trip or external ADC start-of-conversion EV-B.
62 VSS power_in Core and digital I/O ground pin.
63 VDD power_in 1.8-V or 1.9-V core digital power pin.
64 GPIOF6/CANTXA bidirectional GPIO or eCAN transmit data.
65 GPIOF7/CANRXA bidirectional GPIO or eCAN receive data.
66 GPIOG4/SCITXDB bidirectional GPIO or SCI asynchronous serial port transmit data.
67 GPIOG5/SCIRXDB bidirectional GPIO or SCI asynchronous serial port receive data.
68 GPIOA0/PWM1 bidirectional GPIO or PWM output pin #1; internal pullup.
69 GPIOA1/PWM2 bidirectional GPIO or PWM output pin #2; internal pullup.
70 GPIOA2/PWM3 bidirectional GPIO or PWM output pin #3; internal pullup.
71 GPIOA3/PWM4 bidirectional GPIO or PWM output pin #4; internal pullup.
72 GPIOA4/PWM5 bidirectional GPIO or PWM output pin #5; internal pullup.
73 VSS power_in Core and digital I/O ground pin.
74 VDD power_in 1.8-V or 1.9-V core digital power pin.
75 GPIOA5/PWM6 bidirectional GPIO or PWM output pin #6; internal pullup.
76 GPIOA6/T1PWM_T1CMP bidirectional GPIO or timer 1 output.
77 GPIOA7/T2PWM_T2CMP bidirectional GPIO or timer 2 output.
78 GPIOA8/CAP1_QEP1 bidirectional GPIO or capture input #1.
79 GPIOA9/CAP2_QEP2 bidirectional GPIO or capture input #2.
80 GPIOA10/CAP3_QEPI1 bidirectional GPIO or capture input #3.
81 GPIOD0/T1CTRIP_PDPINTA bidirectional GPIO or timer 1 compare output trip.
82 VDD power_in 1.8-V or 1.9-V core digital power pin.
83 VDDIO power_in 3.3-V I/O digital power pin.
84 GPIOD1/T2CTRIP/EVASOC bidirectional GPIO or timer 2 compare output trip or external ADC start-of-conversion EV-A.
85 GPIOA11/TDIRA bidirectional GPIO or timer direction input.
86 GPIOA12/TCLKINA bidirectional GPIO or timer clock input.
87 XCLKOUT output Output clock derived from SYSCLKOUT at the same, 1/2 or 1/4 frequency; reset value is SYSCLKOUT/4 and the pin is not placed in high impedance during reset.
88 VSS power_in Core and digital I/O ground pin.
89 GPIOA13/C1TRIP bidirectional GPIO or compare 1 output trip.
90 GPIOA14/C2TRIP bidirectional GPIO or compare 2 output trip.
91 GPIOA15/C3TRIP bidirectional GPIO or compare 3 output trip.
92 TMS input JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK.
93 TDO tri_state JTAG scan out; the contents of the selected register are shifted out on the falling edge of TCK.
94 VDD power_in 1.8-V or 1.9-V core digital power pin.
95 VSS power_in Core and digital I/O ground pin.
96 TDI input JTAG test data input with internal pullup, clocked into the selected register on a rising edge of TCK.
97 TESTSEL input Test pin reserved for TI with internal pulldown; must be connected to ground.
98 TRST input JTAG test reset with internal pulldown; must be maintained low at all times during normal device operation.
99 TCK input JTAG test clock with internal pullup.
100 EMU0 bidirectional Emulator pin 0 with internal pullup; an external 2.2 kohm to 4.7 kohm pullup resistor is recommended.
101 GPIOF14/XF_XPLLDIS bidirectional XF general-purpose output; sampled during reset to disable the PLL if low, after which HALT and STANDBY modes cannot be used.
102 VDD power_in 1.8-V or 1.9-V core digital power pin.
103 VSS power_in Core and digital I/O ground pin.
104 VDDIO power_in 3.3-V I/O digital power pin.
105 EMU1 bidirectional Emulator pin 1 with internal pullup; an external 2.2 kohm to 4.7 kohm pullup resistor is recommended.
106 GPIOE0/XINT1_XBIO bidirectional GPIO or XINT1 or XBIO input.
107 GPIOE2/XNMI_XINT13 bidirectional GPIO or XNMI or XINT13 input; internal pullup.
108 GPIOE1/XINT2_ADCSOC bidirectional GPIO or XINT2 or ADC start-of-conversion.
109 VSS power_in Core and digital I/O ground pin.
110 VDD power_in 1.8-V or 1.9-V core digital power pin.
111 GPIOF4/SCITXDA bidirectional GPIO or SCI asynchronous serial port transmit data.
112 GPIOF5/SCIRXDA bidirectional GPIO or SCI asynchronous serial port receive data.
113 XRS bidirectional Device reset input and watchdog reset output; open-drain with internal 100 uA pullup, driven low for 512 XCLKIN cycles on a watchdog reset.
114 VDD1 power_in ADC digital 1.8-V (or 1.9-V) supply.
115 VSS1 power_in ADC digital ground.
116 ADCBGREFIN unconnected Test pin reserved for TI; must be left unconnected.
117 VSSA2 power_in ADC analog ground.
118 VDDA2 power_in ADC analog 3.3-V supply.
119 ADCINA7 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
120 ADCINA6 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
121 ADCINA5 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
122 ADCINA4 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
123 ADCINA3 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
124 ADCINA2 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
125 ADCINA1 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
126 ADCINA0 input Analog input 0-3 V with respect to ADCLO for Sample-and-Hold A; ADC pins should not be driven before VDDA1, VDDA2 and VDDAIO are fully powered up.
127 ADCLO input Common low side analog input; connect to analog ground.
128 VSSAIO power_in Analog I/O ground pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-128(14x14)
Category Embedded Processors & Controllers
Pins 128

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDIO -0.3 4.6 V 19
Supply voltage VDD -0.5 2.5 V 19
Input voltage VIN -0.3 4.6 V 19
Output voltage VO -0.3 4.6 V 19
Input clamp current IIK -20 20 mA VIN < 0 or VIN > VDDIO 19
Output clamp current IOK -20 20 mA VO < 0 or VO > VDDIO 19
Operating ambient temperature TA -40 85 °C A version (PBK) 19
Junction temperature TJ -40 150 °C 19
Storage temperature Tstg -65 150 °C 19
Device supply voltage, I/O VDDIO 3.14 3.3 3.47 V 21
Device supply voltage, CPU VDD, VDD1 1.71 1.8 1.89 V 1.8 V (135 MHz) 21
Device supply voltage, CPU VDD, VDD1 1.81 1.9 2 V 1.9 V (150 MHz) 21
Supply ground VSS 0 V 21
ADC supply voltage VDDA1, VDDA2, AVDDREFBG, VDDAIO 3.14 3.3 3.47 V 21
Flash programming supply voltage VDD3VFL 3.14 3.3 3.47 V 21
Device clock frequency (system clock) fSYSCLKOUT 2 150 MHz VDD = 1.9 V ± 5% 21
Device clock frequency (system clock) fSYSCLKOUT 2 135 MHz VDD = 1.8 V ± 5% 21
Low-level input voltage VIL 0.8 V All inputs except X1/XCLKIN 21
High-level input voltage VIH 2 V All inputs except X1/XCLKIN 21
High-level output source current IOH -4 mA VOH = 2.4 V, All I/Os except Group 2 21
High-level output source current IOH -8 mA VOH = 2.4 V, Group 2 21
Low-level output sink current IOL 4 mA VOL = VOL MAX, All I/Os except Group 2 21
Low-level output sink current IOL 8 mA VOL = VOL MAX, Group 2 21
Ambient temperature TA -40 85 °C A version 21
High-level output voltage VOH 2.4 V IOH = IOH MAX 25
Low-level output voltage VOL 0.4 V IOL = IOL MAX 25
Input current (low level) IIL -80 -140 -190 µA With pullup, VDDIO = 3.3 V, VIN = 0 V, all I/Os (including XRS) except EVB 25
Input current (low level) IIL -13 -25 -35 µA With pullup, VDDIO = 3.3 V, VIN = 0 V, GPIOB/EVB 25
Input current (low level) IIL -2 2 µA With pulldown, VDDIO = 3.3 V, VIN = 0 V 25
Input current (high level) IIH -2 2 µA With pullup, VDDIO = 3.3 V, VIN = VDD 25
Input current (high level) IIH 28 50 80 µA With pulldown, VDDIO = 3.3 V, VIN = VDD 25
Leakage current (high-impedance state) IOZ -2 2 µA VO = VDDIO or 0 V, pins without internal PU/PD 25
Junction-to-case thermal resistance RΘJC 10.76 °C/W 128-pin PBK package 26
Junction-to-free air thermal resistance RΘJA 41.65 °C/W 128-pin PBK package 26
Junction-to-package top PsiJT 0.271 °C/W 128-pin PBK package 26
Operational current, IDD IDD 195 230 mA Operational, 150 MHz SYSCLKOUT, max at 125 °C 22
Operational current, IDDIO IDDIO 15 30 mA Operational, 150 MHz SYSCLKOUT, max at 125 °C 22
Operational current, IDD3VFL IDD3VFL 40 45 mA Operational, 150 MHz SYSCLKOUT, max at 125 °C 22
Operational current, IDDA IDDA 40 50 mA Operational, 150 MHz SYSCLKOUT, max at 125 °C 22
IDLE current, IDD IDD 125 150 mA IDLE mode, flash powered down, XCLKOUT off 22
IDLE current, IDDIO IDDIO 5 10 mA IDLE mode, flash powered down, XCLKOUT off 22
IDLE current, IDD3VFL IDD3VFL 2 4 µA IDLE mode, flash powered down, XCLKOUT off 22
IDLE current, IDDA IDDA 1 20 µA IDLE mode, flash powered down, XCLKOUT off 22
STANDBY current, IDD IDD 5 10 mA STANDBY mode, peripheral clocks off 22
STANDBY current, IDDIO IDDIO 5 20 µA STANDBY mode, peripheral clocks off 22
STANDBY current, IDD3VFL IDD3VFL 2 4 µA STANDBY mode, peripheral clocks off 22
STANDBY current, IDDA IDDA 1 20 µA STANDBY mode, peripheral clocks off 22

CAD (KiCad official)

  • Symbol: TMS320F2810PBKA
  • Footprint: Package_QFP:LQFP-128_14x14mm_P0.4mm
  • 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2810pbka-etched.step / tms320f2810pbka-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2810pbka.step / tms320f2810pbka.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (174 pp, sha256 a2b8a20dd7eb198d, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF