Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TMS320F2809PZA

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F2809PZA from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12 bidirectional General-purpose input/output 12 with internal pullup enabled at reset; alternate functions: Trip Zone input 1, Enhanced CAN-B transmit, or SPI-B Slave in/Master out.
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O power pin (3.3 V).
4 GPIO29 output General-purpose input/output 29 with 8-mA typical drive; alternate functions: SCI transmit data (output) or Trip Zone input 6; internal pullup enabled at reset.
5 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose input/output 33 with I2C clock open-drain bidirectional port; alternate functions: Enhanced PWM external sync pulse output or ADC start-of-conversion B; internal pullup enabled at reset.
6 GPIO30/CANRXA input General-purpose input/output 30 with 8-mA typical drive; alternate function: Enhanced CAN-A receive data; internal pullup enabled at reset.
7 GPIO31/CANTXA output General-purpose input/output 31 with 8-mA typical drive; alternate function: Enhanced CAN-A transmit data; internal pullup enabled at reset.
8 GPIO14 output General-purpose input/output 14; alternate functions: Trip Zone input 3, SCI-B transmit, or SPI-B clock; internal pullup enabled at reset.
9 GPIO15 input General-purpose input/output 15; alternate functions: Trip Zone input 4, SCI-B receive, or SPI-B slave transmit enable; internal pullup enabled at reset.
10 VDD power_in CPU and logic digital power pin (1.8 V core supply).
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC analog power pin (1.8 V).
13 VSS1AGND power_in ADC analog ground pin.
14 VSSA2 power_in ADC analog ground pin.
15 VDDA2 power_in ADC analog power pin (3.3 V).
16 ADCINA7 input ADC Group A channel 7 analog input (0.0 V to 3.0 V with respect to ADCLO).
17 ADCINA6 input ADC Group A channel 6 analog input (0.0 V to 3.0 V with respect to ADCLO).
18 ADCINA5 input ADC Group A channel 5 analog input (0.0 V to 3.0 V with respect to ADCLO).
19 ADCINA4 input ADC Group A channel 4 analog input (0.0 V to 3.0 V with respect to ADCLO).
20 ADCINA3 input ADC Group A channel 3 analog input (0.0 V to 3.0 V with respect to ADCLO).
21 ADCINA2 input ADC Group A channel 2 analog input (0.0 V to 3.0 V with respect to ADCLO).
22 ADCINA1 input ADC Group A channel 1 analog input (0.0 V to 3.0 V with respect to ADCLO).
23 ADCINA0 input ADC Group A channel 0 analog input (0.0 V to 3.0 V with respect to ADCLO).
24 ADCLO input ADC low reference input; connect to analog ground.
25 VSSAIO power_in ADC analog I/O ground pin.
26 VDDAIO power_in ADC analog I/O power pin (3.3 V).
27 ADCINB0 input ADC Group B channel 0 analog input (0.0 V to 3.0 V with respect to ADCLO).
28 ADCINB1 input ADC Group B channel 1 analog input (0.0 V to 3.0 V with respect to ADCLO).
29 ADCINB2 input ADC Group B channel 2 analog input (0.0 V to 3.0 V with respect to ADCLO).
30 ADCINB3 input ADC Group B channel 3 analog input (0.0 V to 3.0 V with respect to ADCLO).
31 ADCINB4 input ADC Group B channel 4 analog input (0.0 V to 3.0 V with respect to ADCLO).
32 ADCINB5 input ADC Group B channel 5 analog input (0.0 V to 3.0 V with respect to ADCLO).
33 ADCINB6 input ADC Group B channel 6 analog input (0.0 V to 3.0 V with respect to ADCLO).
34 ADCINB7 input ADC Group B channel 7 analog input (0.0 V to 3.0 V with respect to ADCLO).
35 ADCREFIN input ADC external reference input; float or connect to ground if internal reference is used.
36 ADCREFM output ADC internal reference medium output requiring low ESR ceramic bypass capacitor (2.2 μF, <1.5 Ω) to analog ground.
37 ADCREFP output ADC internal reference positive output requiring low ESR ceramic bypass capacitor (2.2 μF, <1.5 Ω) to analog ground.
38 ADCRESEXT passive ADC external current bias resistor pin; connect 22-kΩ resistor to analog ground.
39 VSS2AGND power_in ADC analog ground pin.
40 VDD2A18 power_in ADC analog power pin (1.8 V).
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and logic digital power pin (1.8 V core supply).
43 GPIO34 bidirectional General-purpose input/output 34 with internal pullup enabled at reset; no peripheral alternate functions.
44 GPIO1/EPWM1B/SPISIMOD bidirectional General-purpose input/output 1; alternate functions: Enhanced PWM1 output B or SPI-D slave in/master out; pullup not enabled at reset.
45 GPIO2/EPWM2A output General-purpose input/output 2; alternate function: Enhanced PWM2 output A and HRPWM channel; pullup not enabled at reset.
46 VDDIO power_in Digital I/O power pin (3.3 V).
47 GPIO0/EPWM1A output General-purpose input/output 0; alternate function: Enhanced PWM1 output A and HRPWM channel; pullup not enabled at reset.
48 GPIO3/EPWM2B/SPISOMID bidirectional General-purpose input/output 3; alternate functions: Enhanced PWM2 output B or SPI-D slave out/master in; pullup not enabled at reset.
49 VSS power_in Digital ground pin.
50 GPIO16/SPISIMOA/CANTXB/TZ5 bidirectional General-purpose input/output 16; alternate functions: SPI-A slave in/master out, Enhanced CAN-B transmit, or Trip Zone input 5; internal pullup enabled at reset.
51 GPIO4/EPWM3A output General-purpose input/output 4; alternate function: Enhanced PWM3 output A and HRPWM channel; pullup not enabled at reset.
52 GPIO17/SPISOMIA/CANRXB/TZ6 bidirectional General-purpose input/output 17; alternate functions: SPI-A slave out/master in, Enhanced CAN-B receive, or Trip Zone input 6; internal pullup enabled at reset.
53 GPIO5/EPWM3B/SPICLKD/ECAP1 bidirectional General-purpose input/output 5; alternate functions: Enhanced PWM3 output B, SPI-D clock, or Enhanced capture input/output 1; pullup not enabled at reset.
54 GPIO18/SPICLKA/SCITXDB bidirectional General-purpose input/output 18; alternate functions: SPI-A clock or SCI-B transmit; internal pullup enabled at reset.
55 VSS power_in Digital ground pin.
56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose input/output 6; alternate functions: Enhanced PWM4 output A with HRPWM, external ePWM sync pulse input, or external ePWM sync pulse output; pullup not enabled at reset.
57 GPIO19/SPISTEA/SCIRXDB input General-purpose input/output 19; alternate functions: SPI-A slave transmit enable or SCI-B receive; internal pullup enabled at reset.
58 GPIO7/EPWM4B/SPISTED/ECAP2 bidirectional General-purpose input/output 7; alternate functions: Enhanced PWM4 output B, SPI-D slave transmit enable, or Enhanced capture input/output 2; pullup not enabled at reset.
59 VDD power_in CPU and logic digital power pin (1.8 V core supply).
60 GPIO8/EPWM5A/CANTXB/ADCSOCAO output General-purpose input/output 8; alternate functions: Enhanced PWM5 output A with HRPWM, Enhanced CAN-B transmit, or ADC start-of-conversion A; pullup not enabled at reset.
61 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional General-purpose input/output 9; alternate functions: Enhanced PWM5 output B, SCI-B transmit, or Enhanced capture input/output 3; pullup not enabled at reset.
62 VSS power_in Digital ground pin.
63 GPIO20/EQEP1A/SPISIMOC/CANTXB bidirectional General-purpose input/output 20; alternate functions: Enhanced QEP1 input A, SPI-C slave in/master out, or Enhanced CAN-B transmit; internal pullup enabled at reset.
64 GPIO10/EPWM6A/CANRXB/ADCSOCBO output General-purpose input/output 10; alternate functions: Enhanced PWM6 output A with HRPWM, Enhanced CAN-B receive, or ADC start-of-conversion B; pullup not enabled at reset.
65 VDDIO power_in Digital I/O power pin (3.3 V).
66 XCLKOUT output Output clock derived from SYSCLKOUT with programmable division (÷1, ÷2, ÷4) or disable; can be turned off by register control.
67 GPIO21/EQEP1B/SPISOMIC/CANRXB input General-purpose input/output 21; alternate functions: Enhanced QEP1 input B, SPI-C master in/slave out, or Enhanced CAN-B receive; internal pullup enabled at reset.
68 VDD power_in CPU and logic digital power pin (1.8 V core supply).
69 VSS power_in Digital ground pin.
70 GPIO11/EPWM6B/SCIRXDB/ECAP4 input General-purpose input/output 11; alternate functions: Enhanced PWM6 output B, SCI-B receive, or Enhanced CAP input/output 4; pullup not enabled at reset.
71 GPIO22/EQEP1S/SPICLKC/SCITXDB bidirectional General-purpose input/output 22; alternate functions: Enhanced QEP1 strobe, SPI-C clock, or SCI-B transmit; internal pullup enabled at reset.
72 GPIO23/EQEP1I/SPISTEC/SCIRXDB bidirectional General-purpose input/output 23; alternate functions: Enhanced QEP1 index, SPI-C slave transmit enable, or SCI-B receive; internal pullup enabled at reset.
73 TDI input JTAG test data input with internal pullup; clocked into selected register on rising edge of TCK.
74 TMS input JTAG test-mode select with internal pullup; serial control input clocked into TAP controller on rising edge of TCK.
75 TCK input JTAG test clock with internal pullup.
76 TDO tri_state JTAG scan out, test data output with 8 mA drive; contents of selected register shifted out on falling edge of TCK.
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device reset input and watchdog reset output with open-drain output buffer and internal pullup; drives PC to 0x3FFFC0 on reset.
79 GPIO27/ECAP4/EQEP2S/SPISTEB bidirectional General-purpose input/output 27; alternate functions: Enhanced capture input/output 4, Enhanced QEP2 strobe, or SPI-B slave transmit enable; internal pullup enabled at reset.
80 EMU0 bidirectional Emulator pin 0 with 8 mA drive and internal pullup; used as emulator interrupt or for boundary-scan mode entry when combined with EMU1; external pullup resistor (2.2-4.7 kΩ) recommended.
81 EMU1 bidirectional Emulator pin 1 with 8 mA drive and internal pullup; used as emulator interrupt or for boundary-scan mode entry when combined with EMU0; external pullup resistor (2.2-4.7 kΩ) recommended.
82 VDDIO power_in Digital I/O power pin (3.3 V).
83 GPIO24/ECAP1/EQEP2A/SPISIMOB bidirectional General-purpose input/output 24; alternate functions: Enhanced capture input/output 1, Enhanced QEP2 input A, or SPI-B slave in/master out; internal pullup enabled at reset.
84 TRST input JTAG test reset with internal pulldown; active-high test pin, must be maintained low during normal operation; external pulldown resistor (2.2 kΩ typical) required.
85 VDD power_in CPU and logic digital power pin (1.8 V core supply).
86 X2 output Internal oscillator output; quartz crystal or ceramic resonator may be connected across X1 and X2; leave unconnected if not used.
87 VSS power_in Digital ground pin.
88 X1 input Internal/external oscillator input referenced to 1.8-V core supply; quartz crystal, ceramic resonator, or 1.8-V external oscillator may be connected.
89 VSS power_in Digital ground pin.
90 XCLKIN input External oscillator input for 3.3-V external clock source; tie to ground if crystal or 1.8-V oscillator is used on X1.
91 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional General-purpose input/output 25; alternate functions: Enhanced capture input/output 2, Enhanced QEP2 input B, or SPI-B master in/slave out; internal pullup enabled at reset.
92 GPIO28/SCIRXDA/TZ5 input General-purpose input/output 28 with 8-mA typical output buffer; alternate functions: SCI receive data or Trip Zone input 5; internal pullup enabled at reset.
93 VDD power_in CPU and logic digital power pin (1.8 V core supply).
94 VSS power_in Digital ground pin.
95 GPIO13 input General-purpose input/output 13; alternate functions: Trip Zone input 2, Enhanced CAN-B receive, or SPI-B slave out/master in; internal pullup enabled at reset.
96 VDD3VFL power_in 3.3-V Flash core power pin; must be connected to 3.3 V at all times.
97 TEST1 unconnected Test pin reserved for Texas Instruments; must be left unconnected.
98 TEST2 unconnected Test pin reserved for Texas Instruments; must be left unconnected.
99 GPIO26/ECAP3/EQEP2I/SPICLKB bidirectional General-purpose input/output 26; alternate functions: Enhanced capture input/output 3, Enhanced QEP2 index, or SPI-B clock; internal pullup enabled at reset.
100 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose input/output 32 with I2C data open-drain bidirectional port; alternate functions: Enhanced PWM external sync pulse input or ADC start-of-conversion A; internal pullup enabled at reset.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F2809PZA
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2809pza-etched.step / tms320f2809pza-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2809pza.step / tms320f2809pza.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF