component
TMS320F2808PZA
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F2808PZA
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
TMS320F2808PZA from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO12 | bidirectional | General-purpose input/output 12 with tri-state capability and internal pullup enabled at reset; alternate functions: TZ1 (Trip Zone input 1), CANTXB (CAN-B transmit), SPISIMOB (SPI-B slave in, master out). |
| 2 | VSS | power_in | Digital ground connection. |
| 3 | VDDIO | power_in | Digital I/O power pin at 3.3 V. |
| 4 | GPIO29 | bidirectional | General-purpose input/output 29 with 8-mA typical output buffer and tri-state capability with internal pullup enabled at reset; alternate functions: SCITXDA (SCI transmit data), TZ6 (Trip Zone 6 input). |
| 5 | GPIO33 | bidirectional | General-purpose input/output 33 with open-drain bidirectional I2C clock port; alternate functions: SCLA (I2C clock), EPWMSYNCO (Enhanced PWM external sync pulse output), ADCSOCBO (ADC start-of-conversion B). |
| 6 | GPIO30 | bidirectional | General-purpose input/output 30 with 8-mA typical output buffer and tri-state capability with internal pullup enabled at reset; alternate function: CANRXA (Enhanced CAN-A receive data). |
| 7 | GPIO31 | bidirectional | General-purpose input/output 31 with 8-mA typical output buffer and tri-state capability with internal pullup enabled at reset; alternate function: CANTXA (Enhanced CAN-A transmit data). |
| 8 | GPIO14 | bidirectional | General-purpose input/output 14 with tri-state capability and internal pullup enabled at reset; alternate functions: TZ3 (Trip Zone input 3), SCITXDB (SCI-B transmit), SPICLKB (SPI-B clock). |
| 9 | GPIO15 | bidirectional | General-purpose input/output 15 with tri-state capability and internal pullup enabled at reset; alternate functions: TZ4 (Trip Zone input 4), SCIRXDB (SCI-B receive), SPISTEB (SPI-B slave transmit enable). |
| 10 | VDD | power_in | CPU and logic digital power pin at 1.8 V. |
| 11 | VSS | power_in | Digital ground connection. |
| 12 | VDD1A18 | power_in | ADC analog power pin at 1.8 V. |
| 13 | VSS1AGND | power_in | ADC analog ground pin. |
| 14 | VSSA2 | power_in | ADC analog ground pin. |
| 15 | VDDA2 | power_in | ADC analog power pin at 3.3 V. |
| 16 | ADCINA7 | input | ADC Group A, Channel 7 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 17 | ADCINA6 | input | ADC Group A, Channel 6 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 18 | ADCINA5 | input | ADC Group A, Channel 5 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 19 | ADCINA4 | input | ADC Group A, Channel 4 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 20 | ADCINA3 | input | ADC Group A, Channel 3 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 21 | ADCINA2 | input | ADC Group A, Channel 2 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 22 | ADCINA1 | input | ADC Group A, Channel 1 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 23 | ADCINA0 | input | ADC Group A, Channel 0 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 24 | ADCLO | input | ADC low reference input; connect to analog ground for 0.0 V reference. |
| 25 | VSSAIO | power_in | ADC analog I/O ground pin. |
| 26 | VDDAIO | power_in | ADC analog I/O power pin at 3.3 V. |
| 27 | ADCINB0 | input | ADC Group B, Channel 0 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 28 | ADCINB1 | input | ADC Group B, Channel 1 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 29 | ADCINB2 | input | ADC Group B, Channel 2 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 30 | ADCINB3 | input | ADC Group B, Channel 3 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 31 | ADCINB4 | input | ADC Group B, Channel 4 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 32 | ADCINB5 | input | ADC Group B, Channel 5 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 33 | ADCINB6 | input | ADC Group B, Channel 6 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 34 | ADCINB7 | input | ADC Group B, Channel 7 analog input (0.0 V to 3.0 V range with respect to ADCLO). |
| 35 | ADCREFIN | input | External ADC reference input; float or ground if internal reference is used. |
| 36 | ADCREFM | output | Internal ADC reference medium output requiring 2.2 μF low-ESR ceramic bypass capacitor to analog ground. |
| 37 | ADCREFP | output | Internal ADC reference positive output requiring 2.2 μF low-ESR ceramic bypass capacitor to analog ground. |
| 38 | ADCRESEXT | passive | ADC external current bias resistor connection; connect 22-kΩ resistor to analog ground. |
| 39 | VSS2AGND | power_in | ADC analog ground pin. |
| 40 | VDD2A18 | power_in | ADC analog power pin at 1.8 V. |
| 41 | VSS | power_in | Digital ground connection. |
| 42 | VDD | power_in | CPU and logic digital power pin at 1.8 V. |
| 43 | GPIO34 | bidirectional | General-purpose input/output 34 with tri-state capability and internal pullup enabled at reset. |
| 44 | GPIO1 | bidirectional | General-purpose input/output 1 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM1B (Enhanced PWM1 output B), SPISIMOD (SPI-D slave in, master out). |
| 45 | GPIO2 | bidirectional | General-purpose input/output 2 with tri-state capability; internal pullup not enabled at reset; alternate function: EPWM2A (Enhanced PWM2 output A and HRPWM channel). |
| 46 | VDDIO | power_in | Digital I/O power pin at 3.3 V. |
| 47 | GPIO0 | bidirectional | General-purpose input/output 0 with tri-state capability; internal pullup not enabled at reset; alternate function: EPWM1A (Enhanced PWM1 output A and HRPWM channel). |
| 48 | GPIO3 | bidirectional | General-purpose input/output 3 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM2B (Enhanced PWM2 output B), SPISOMID (SPI-D slave out, master in). |
| 49 | VSS | power_in | Digital ground connection. |
| 50 | GPIO16 | bidirectional | General-purpose input/output 16 with tri-state capability and internal pullup enabled at reset; alternate functions: SPISIMOA (SPI-A slave in, master out), CANTXB (CAN-B transmit), TZ5 (Trip Zone input 5). |
| 51 | GPIO4 | bidirectional | General-purpose input/output 4 with tri-state capability; internal pullup not enabled at reset; alternate function: EPWM3A (Enhanced PWM3 output A and HRPWM channel). |
| 52 | GPIO17 | bidirectional | General-purpose input/output 17 with tri-state capability and internal pullup enabled at reset; alternate functions: SPISOMIA (SPI-A slave out, master in), CANRXB (CAN-B receive), TZ6 (Trip Zone input 6). |
| 53 | GPIO5 | bidirectional | General-purpose input/output 5 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM3B (Enhanced PWM3 output B), SPICLKD (SPI-D clock), ECAP1 (Enhanced capture input/output 1). |
| 54 | GPIO18 | bidirectional | General-purpose input/output 18 with tri-state capability and internal pullup enabled at reset; alternate functions: SPICLKA (SPI-A clock input/output), SCITXDB (SCI-B transmit). |
| 55 | VSS | power_in | Digital ground connection. |
| 56 | GPIO6 | bidirectional | General-purpose input/output 6 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM4A (Enhanced PWM4 output A and HRPWM channel), EPWMSYNCI (External ePWM sync pulse input), EPWMSYNCO (External ePWM sync pulse output). |
| 57 | GPIO19 | bidirectional | General-purpose input/output 19 with tri-state capability and internal pullup enabled at reset; alternate functions: SPISTEA (SPI-A slave transmit enable input/output), SCIRXDB (SCI-B receive). |
| 58 | GPIO7 | bidirectional | General-purpose input/output 7 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM4B (Enhanced PWM4 output B), SPISTED (SPI-D slave transmit enable), ECAP2 (Enhanced capture input/output 2). |
| 59 | VDD | power_in | CPU and logic digital power pin at 1.8 V. |
| 60 | GPIO8 | bidirectional | General-purpose input/output 8 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM5A (Enhanced PWM5 output A and HRPWM channel), CANTXB (CAN-B transmit), ADCSOCAO (ADC start-of-conversion A). |
| 61 | GPIO9 | bidirectional | General-purpose input/output 9 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM5B (Enhanced PWM5 output B), SCITXDB (SCI-B transmit data), ECAP3 (Enhanced capture input/output 3). |
| 62 | VSS | power_in | Digital ground connection. |
| 63 | GPIO20 | bidirectional | General-purpose input/output 20 with tri-state capability and internal pullup enabled at reset; alternate functions: EQEP1A (Enhanced QEP1 input A), SPISIMOC (SPI-C slave in, master out), CANTXB (CAN-B transmit). |
| 64 | GPIO10 | bidirectional | General-purpose input/output 10 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM6A (Enhanced PWM6 output A and HRPWM channel), CANRXB (CAN-B receive), ADCSOCBO (ADC start-of-conversion B). |
| 65 | VDDIO | power_in | Digital I/O power pin at 3.3 V. |
| 66 | XCLKOUT | tri_state | External output clock derived from SYSCLKOUT at frequency controlled by XCLKOUTDIV register bits; default reset value is SYSCLKOUT/4 with 8-mA drive capability and tri-state control. |
| 67 | GPIO21 | bidirectional | General-purpose input/output 21 with tri-state capability and internal pullup enabled at reset; alternate functions: EQEP1B (Enhanced QEP1 input B), SPISOMIC (SPI-C master in, slave out), CANRXB (CAN-B receive). |
| 68 | VDD | power_in | CPU and logic digital power pin at 1.8 V. |
| 69 | VSS | power_in | Digital ground connection. |
| 70 | GPIO11 | bidirectional | General-purpose input/output 11 with tri-state capability; internal pullup not enabled at reset; alternate functions: EPWM6B (Enhanced PWM6 output B), SCIRXDB (SCI-B receive data), ECAP4 (Enhanced CAP Input/Output 4). |
| 71 | GPIO22 | bidirectional | General-purpose input/output 22 with tri-state capability and internal pullup enabled at reset; alternate functions: EQEP1S (Enhanced QEP1 strobe), SPICLKC (SPI-C clock), SCITXDB (SCI-B transmit). |
| 72 | GPIO23 | bidirectional | General-purpose input/output 23 with tri-state capability and internal pullup enabled at reset; alternate functions: EQEP1I (Enhanced QEP1 index), SPISTEC (SPI-C slave transmit enable), SCIRXDB (SCI-B receive). |
| 73 | TDI | input | JTAG test data input with internal pullup; clocked into selected register on rising edge of TCK. |
| 74 | TMS | input | JTAG test-mode select input with internal pullup; serial control input clocked into TAP controller on rising edge of TCK. |
| 75 | TCK | input | JTAG test clock input with internal pullup. |
| 76 | TDO | tri_state | JTAG test data output; scan register contents shifted out on falling edge of TCK with 8-mA drive and tri-state capability. |
| 77 | VSS | power_in | Digital ground connection. |
| 78 | XRS | bidirectional | Device reset input (active low) and watchdog reset output (open-drain) with internal pullup; external device should use open-drain drive when controlling this pin. |
| 79 | GPIO27 | bidirectional | General-purpose input/output 27 with tri-state capability and internal pullup enabled at reset; alternate functions: ECAP4 (Enhanced capture 4), EQEP2S (Enhanced QEP2 strobe), SPISTEB (SPI-B slave transmit enable). |
| 80 | EMU0 | bidirectional | Emulator pin 0; when TRST is driven high, used as interrupt to/from emulator system and defined as input/output through JTAG scan; with EMU0 high and EMU1 low, rising edge on TRST latches device into boundary-scan mode; requires external pullup resistor (2.2 kΩ to 4.7 kΩ recommended); tri-state capable with 8-mA drive. |
| 81 | EMU1 | bidirectional | Emulator pin 1; when TRST is driven high, used as interrupt to/from emulator system and defined as input/output through JTAG scan; with EMU0 high and EMU1 low, rising edge on TRST latches device into boundary-scan mode; requires external pullup resistor (2.2 kΩ to 4.7 kΩ recommended); tri-state capable with 8-mA drive. |
| 82 | VDDIO | power_in | Digital I/O power pin at 3.3 V. |
| 83 | GPIO24 | bidirectional | General-purpose input/output 24 with tri-state capability and internal pullup enabled at reset; alternate functions: ECAP1 (Enhanced capture 1), EQEP2A (Enhanced QEP2 input A), SPISIMOB (SPI-B slave in, master out). |
| 84 | TRST | input | JTAG test reset input with internal pulldown (active high); must be maintained low during normal device operation and requires external pulldown resistor (2.2 kΩ recommended); drives TRST high gives scan system control of device operations. |
| 85 | VDD | power_in | CPU and logic digital power pin at 1.8 V. |
| 86 | X2 | output | Internal oscillator output; quartz crystal or ceramic resonator may be connected between X1 and X2 pins; leave unconnected if not used. |
| 87 | VSS | power_in | Digital ground connection. |
| 88 | X1 | input | Internal/external oscillator input referenced to 1.8 V core digital power supply; connect quartz crystal or ceramic resonator between X1 and X2, or connect 1.8 V external oscillator to X1 with XCLKIN tied to ground, or tie X1 to ground if 3.3 V external oscillator used with XCLKIN. |
| 89 | VSS | power_in | Digital ground connection. |
| 90 | XCLKIN | input | External oscillator input at 3.3 V logic level; tie X1 pin to ground when using external 3.3 V oscillator on this pin or when using crystal/resonator; tie XCLKIN to ground when using 1.8 V external oscillator on X1 pin. |
| 91 | GPIO25 | bidirectional | General-purpose input/output 25 with tri-state capability and internal pullup enabled at reset; alternate functions: ECAP2 (Enhanced capture 2), EQEP2B (Enhanced QEP2 input B), SPISOMIB (SPI-B master in, slave out). |
| 92 | GPIO28 | bidirectional | General-purpose input/output 28 with 8-mA typical output buffer, tri-state capability and internal pullup enabled at reset; alternate functions: SCIRXDA (SCI receive data), TZ5 (Trip Zone input 5). |
| 93 | VDD | power_in | CPU and logic digital power pin at 1.8 V. |
| 94 | VSS | power_in | Digital ground connection. |
| 95 | GPIO13 | bidirectional | General-purpose input/output 13 with tri-state capability and internal pullup enabled at reset; alternate functions: TZ2 (Trip Zone input 2), CANRXB (CAN-B receive), SPISOMIB (SPI-B slave out, master in). |
| 96 | VDD3VFL | power_in | 3.3 V Flash core power pin; must be connected to 3.3 V at all times; on ROM parts (C280x) this pin should be connected to VDDIO. |
| 97 | TEST1 | unconnected | Test pin reserved for TI internal use; must be left unconnected. |
| 98 | TEST2 | unconnected | Test pin reserved for TI internal use; must be left unconnected. |
| 99 | GPIO26 | bidirectional | General-purpose input/output 26 with tri-state capability and internal pullup enabled at reset; alternate functions: ECAP3 (Enhanced capture 3), EQEP2I (Enhanced QEP2 index), SPICLKB (SPI-B clock). |
| 100 | GPIO32 | bidirectional | General-purpose input/output 32 with open-drain bidirectional I2C data port and tri-state capability with internal pullup enabled at reset; alternate functions: SDAA (I2C data), EPWMSYNCI (Enhanced PWM external sync pulse input), ADCSOCAO (ADC start-of-conversion output). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
TMS320F2808PZA - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
tms320f2808pza-etched.step/tms320f2808pza-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f2808pza.step/tms320f2808pza.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (157 pp, sha256
a13113c4c002c567, retrieved 2026-09-24, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).