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TMS320F2806PZA

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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TMS320F2806PZA

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F2806PZA from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12/TZ1/SPISIMOB bidirectional GPIO12 general-purpose I/O with internal pull-up, configurable as trip zone input 1 or SPI-B slave in/master out.
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O power pin, 3.3 V.
4 GPIO29/SCITXDA/TZ6 bidirectional GPIO29 with 8-mA output buffer, configurable as SCI-A transmit or trip zone input 6.
5 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional GPIO33 I2C clock open-drain bidirectional port, configurable as enhanced PWM sync pulse output or ADC start-of-conversion B output.
6 GPIO30/CANRXA bidirectional GPIO30 with 8-mA output buffer, configurable as enhanced CAN-A receive data input.
7 GPIO31/CANTXA bidirectional GPIO31 with 8-mA output buffer, configurable as enhanced CAN-A transmit data output.
8 GPIO14/TZ3/SPICLKB bidirectional GPIO14 with internal pull-up, configurable as trip zone input 3 or SPI-B clock input/output.
9 GPIO15/TZ4/SPISTEB bidirectional GPIO15 with internal pull-up, configurable as trip zone input 4 or SPI-B slave transmit enable input/output.
10 VDD power_in CPU and logic digital power pin, 1.8 V.
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC analog power pin, 1.8 V.
13 VSS1AGND power_in ADC analog ground pin.
14 VSSA2 power_in ADC analog ground pin.
15 VDDA2 power_in ADC analog power pin, 3.3 V.
16 ADCINA7 input ADC group A channel 7 input, 0 to 3.0 V.
17 ADCINA6 input ADC group A channel 6 input, 0 to 3.0 V.
18 ADCINA5 input ADC group A channel 5 input, 0 to 3.0 V.
19 ADCINA4 input ADC group A channel 4 input, 0 to 3.0 V.
20 ADCINA3 input ADC group A channel 3 input, 0 to 3.0 V.
21 ADCINA2 input ADC group A channel 2 input, 0 to 3.0 V.
22 ADCINA1 input ADC group A channel 1 input, 0 to 3.0 V.
23 ADCINA0 input ADC group A channel 0 input, 0 to 3.0 V.
24 ADCLO input ADC low reference, connect to analog ground.
25 VSSAIO power_in ADC analog I/O ground pin.
26 VDDAIO power_in ADC analog I/O power pin, 3.3 V.
27 ADCINB0 input ADC group B channel 0 input, 0 to 3.0 V.
28 ADCINB1 input ADC group B channel 1 input, 0 to 3.0 V.
29 ADCINB2 input ADC group B channel 2 input, 0 to 3.0 V.
30 ADCINB3 input ADC group B channel 3 input, 0 to 3.0 V.
31 ADCINB4 input ADC group B channel 4 input, 0 to 3.0 V.
32 ADCINB5 input ADC group B channel 5 input, 0 to 3.0 V.
33 ADCINB6 input ADC group B channel 6 input, 0 to 3.0 V.
34 ADCINB7 input ADC group B channel 7 input, 0 to 3.0 V.
35 ADCREFIN input External reference input pin, float or ground if internal reference used.
36 ADCREFM output ADC internal reference medium output requiring 2.2 µF low-ESR bypass capacitor to analog ground.
37 ADCREFP output ADC internal reference positive output requiring 2.2 µF low-ESR bypass capacitor to analog ground.
38 ADCRESEXT passive ADC external current bias resistor connection, connect 22-kΩ resistor to analog ground.
39 VSS2AGND power_in ADC analog ground pin.
40 VDD2A18 power_in ADC analog power pin, 1.8 V.
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and logic digital power pin, 1.8 V.
43 GPIO34 bidirectional GPIO34 general-purpose I/O with internal pull-up.
44 GPIO1/EPWM1B/SPISIMOD bidirectional GPIO1 with internal pull-up, configurable as enhanced PWM1 output B or SPI-D slave in/master out.
45 GPIO2/EPWM2A bidirectional GPIO2 with internal pull-up, configurable as enhanced PWM2 output A and HRPWM channel.
46 VDDIO power_in Digital I/O power pin, 3.3 V.
47 GPIO0/EPWM1A bidirectional GPIO0 with 4-mA output (pull-ups not enabled at reset), configurable as enhanced PWM1 output A and HRPWM channel.
48 GPIO3/EPWM2B/SPISOMID bidirectional GPIO3 with internal pull-up, configurable as enhanced PWM2 output B or SPI-D slave out/master in.
49 VSS power_in Digital ground pin.
50 GPIO16/SPISIMOA/TZ5 bidirectional GPIO16 with internal pull-up, configurable as SPI-A slave in/master out or trip zone input 5.
51 GPIO4/EPWM3A bidirectional GPIO4 with internal pull-up, configurable as enhanced PWM3 output A and HRPWM channel.
52 GPIO17/SPISOMIA/TZ6 bidirectional GPIO17 with internal pull-up, configurable as SPI-A slave out/master in or trip zone input 6.
53 GPIO5/EPWM3B/SPICLKD/ECAP1 bidirectional GPIO5 with internal pull-up, configurable as enhanced PWM3 output B, SPI-D clock, or enhanced capture 1 input/output.
54 GPIO18/SPICLKA/SCITXDB bidirectional GPIO18 with internal pull-up, configurable as SPI-A clock input/output or SCI-B transmit output.
55 VSS power_in Digital ground pin.
56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional GPIO6 with internal pull-up, configurable as enhanced PWM4 output A and HRPWM, external PWM sync pulse input, or output.
57 GPIO19/SPISTEA/SCIRXDB bidirectional GPIO19 with internal pull-up, configurable as SPI-A slave transmit enable input/output or SCI-B receive data input.
58 GPIO7/EPWM4B/SPISTED/ECAP2 bidirectional GPIO7 with internal pull-up, configurable as enhanced PWM4 output B, SPI-D slave transmit enable, or enhanced capture 2 input/output.
59 VDD power_in CPU and logic digital power pin, 1.8 V.
60 GPIO8/EPWM5A/ADCSOCAO bidirectional GPIO8 with internal pull-up, configurable as enhanced PWM5 output A and HRPWM or ADC start-of-conversion A output.
61 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional GPIO9 with internal pull-up, configurable as enhanced PWM5 output B, SCI-B transmit, or enhanced capture 3 input/output.
62 VSS power_in Digital ground pin.
63 GPIO20/EQEP1A/SPISIMOC bidirectional GPIO20 with internal pull-up, configurable as enhanced QEP1 input A or SPI-C slave in/master out.
64 GPIO10/EPWM6A/ADCSOCBO bidirectional GPIO10 with internal pull-up, configurable as enhanced PWM6 output A and HRPWM or ADC start-of-conversion B output.
65 VDDIO power_in Digital I/O power pin, 3.3 V.
66 XCLKOUT output Output clock derived from SYSCLKOUT with 8-mA drive, divisible by 1, 2, 4, or disabled.
67 GPIO21/EQEP1B/SPISOMIC bidirectional GPIO21 with internal pull-up, configurable as enhanced QEP1 input B or SPI-C master in/slave out.
68 VDD power_in CPU and logic digital power pin, 1.8 V.
69 VSS power_in Digital ground pin.
70 GPIO11/EPWM6B/SCIRXDB/ECAP4 bidirectional GPIO11 with internal pull-up, configurable as enhanced PWM6 output B, SCI-B receive data, or enhanced capture 4 input/output.
71 GPIO22/EQEP1S/SPICLKC/SCITXDB bidirectional GPIO22 with internal pull-up, configurable as enhanced QEP1 strobe input/output, SPI-C clock, or SCI-B transmit.
72 GPIO23/EQEP1I/SPISTEC/SCIRXDB bidirectional GPIO23 with internal pull-up, configurable as enhanced QEP1 index input/output, SPI-C slave transmit enable, or SCI-B receive.
73 TDI input JTAG test data input with internal pull-up, clocked into TAP controller on rising edge of TCK.
74 TMS input JTAG test-mode select with internal pull-up, serial control input clocked into TAP controller on TCK rising edge.
75 TCK input JTAG test clock with internal pull-up.
76 TDO tri_state JTAG test data output with 8-mA drive and high impedance, contents of selected register shifted out on TCK falling edge.
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device reset input and watchdog reset output, open-drain with internal pull-up; driven low by DSP for 512 oscillator clock cycles on watchdog reset.
79 GPIO27/ECAP4/EQEP2S/SPISTEB bidirectional GPIO27 with internal pull-up, configurable as enhanced capture 4, enhanced QEP2 strobe, or SPI-B slave transmit enable.
80 EMU0 bidirectional Emulator pin 0, input/output when TRST driven high for emulator communication or boundary-scan mode entry.
81 EMU1 bidirectional Emulator pin 1, input/output when TRST driven high for emulator communication or boundary-scan mode entry.
82 VDDIO power_in Digital I/O power pin, 3.3 V.
83 GPIO24/ECAP1/EQEP2A/SPISIMOB bidirectional GPIO24 with internal pull-up, configurable as enhanced capture 1, enhanced QEP2 input A, or SPI-B slave in/master out.
84 TRST input JTAG test reset with internal pull-down, active high to enable scan system control; external pull-down resistor (2.2 kΩ typical) required during normal operation.
85 VDD power_in CPU and logic digital power pin, 1.8 V.
86 X2 output Internal oscillator output for crystal or ceramic resonator connection across X1/X2; leave unconnected if unused.
87 VSS power_in Digital ground pin.
88 X1 input Internal/external oscillator input, referenced to 1.8 V core supply for crystal/resonator or 1.8-V oscillator connection; tie to GND if using 3.3-V external oscillator on XCLKIN.
89 VSS power_in Digital ground pin.
90 XCLKIN input External oscillator input for 3.3-V oscillator connection; tie to GND if using crystal/resonator or 1.8-V oscillator on X1.
91 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional GPIO25 with internal pull-up, configurable as enhanced capture 2, enhanced QEP2 input B, or SPI-B master in/slave out.
92 GPIO28/SCIRXDA/TZ5 bidirectional GPIO28 with 8-mA output buffer and internal pull-up, configurable as SCI-A receive or trip zone input 5.
93 VDD power_in CPU and logic digital power pin, 1.8 V.
94 VSS power_in Digital ground pin.
95 GPIO13/TZ2/SPISOMIB bidirectional GPIO13 with internal pull-up, configurable as trip zone input 2 or SPI-B slave out/master in.
96 VDD3VFL power_in 3.3-V Flash core power pin, always connect to 3.3 V.
97 TEST1 unconnected Test pin reserved for Texas Instruments, must be left unconnected.
98 TEST2 unconnected Test pin reserved for Texas Instruments, must be left unconnected.
99 GPIO26/ECAP3/EQEP2I/SPICLKB bidirectional GPIO26 with internal pull-up, configurable as enhanced capture 3, enhanced QEP2 index, or SPI-B clock input/output.
100 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional GPIO32 with internal pull-up, configurable as I2C data open-drain bidirectional port, enhanced PWM sync pulse input, or ADC start-of-conversion output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F2806PZA
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2806pza-etched.step / tms320f2806pza-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2806pza.step / tms320f2806pza.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-09-29, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF