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TMS320F28069UPZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS320F28069UPZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F28069UPZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO42 bidirectional General-purpose I/O 42 (default GPIO at reset) with alternate functions EPWM8A, TZ1 and COMP1OUT.
2 GPIO23 bidirectional General-purpose I/O 23 (default GPIO at reset) with alternate functions EQEP1I, MFSXA and SCIRXDB.
3 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF capacitor between each VDD pin and ground.
4 VSS power_in Digital ground pin.
5 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
6 GPIO20 bidirectional General-purpose I/O 20 with alternate functions EQEP1A, MDXA and COMP1OUT.
7 GPIO21 bidirectional General-purpose I/O 21 with alternate functions EQEP1B, MDRA and COMP2OUT.
8 GPIO43 bidirectional General-purpose I/O 43 with alternate functions EPWM8B, TZ2 and COMP2OUT.
9 GPIO4 bidirectional General-purpose I/O 4 with alternate function EPWM3A (HRPWM channel).
10 GPIO5 bidirectional General-purpose I/O 5 with alternate functions EPWM3B, SPISIMOA and ECAP1.
11 XRS bidirectional Open-drain device reset input and watchdog reset output with internal pullup; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and the pin is driven low for 512 OSCCLK cycles during watchdog reset.
12 TRST input JTAG test reset with internal pulldown; must be maintained low during normal operation and an external pulldown (2.2 kΩ generally adequate) is required.
13 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
14 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF capacitor between each VDD pin and ground.
15 VSS power_in Digital ground pin.
16 ADCINA7 input ADC group A, channel 7 analog input.
17 ADCINA6 input ADC group A, channel 6 analog input, also COMP3A comparator input and AIO6 analog I/O.
18 ADCINA5 input ADC group A, channel 5 analog input.
19 ADCINA4 input ADC group A, channel 4 analog input, also COMP2A comparator input and AIO4 analog I/O.
20 ADCINA3 input ADC group A, channel 3 analog input.
21 ADCINA2 input ADC group A, channel 2 analog input, also COMP1A comparator input and AIO2 analog I/O.
22 ADCINA1 input ADC group A, channel 1 analog input.
23 ADCINA0 input ADC group A, channel 0 analog input; ADC full-scale range is 0 V to 3.3 V in internal reference mode.
24 VREFHI input ADC external reference high, used only in ADC external reference mode; VREFHI must not exceed VDDA.
25 VDDA power_in Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin.
26 VSSA power_in Analog ground pin.
27 VREFLO input ADC external reference low.
28 ADCINB0 input ADC group B, channel 0 analog input.
29 ADCINB1 input ADC group B, channel 1 analog input.
30 ADCINB2 input ADC group B, channel 2 analog input, also COMP1B comparator input and AIO10 analog I/O.
31 ADCINB3 input ADC group B, channel 3 analog input.
32 ADCINB4 input ADC group B, channel 4 analog input, also COMP2B comparator input and AIO12 analog I/O.
33 ADCINB5 input ADC group B, channel 5 analog input.
34 ADCINB6 input ADC group B, channel 6 analog input, also COMP3B comparator input and AIO14 analog I/O.
35 ADCINB7 input ADC group B, channel 7 analog input.
36 VSS power_in Digital ground pin.
37 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF capacitor between each VDD pin and ground.
38 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
39 GPIO25 bidirectional General-purpose I/O 25 with alternate functions ECAP2, EQEP2B (PZ/PZP only) and SPISOMIB.
40 GPIO31 bidirectional General-purpose I/O 31 with alternate functions CANTXA, EQEP2S (PZ/PZP only) and EPWM8A.
41 GPIO30 bidirectional General-purpose I/O 30 with alternate functions CANRXA, EQEP2I (PZ/PZP only) and EPWM7A.
42 GPIO50 bidirectional General-purpose I/O 50 with alternate functions EQEP1A, MDXA and TZ1.
43 GPIO29 bidirectional General-purpose I/O 29 with alternate functions SCITXDA, SCLA (open-drain I2C clock) and TZ3.
44 GPIO12 bidirectional General-purpose I/O 12 with alternate functions TZ1, SCITXDA and SPISIMOB.
45 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
46 VDD3VFL power_in 3.3-V flash core power pin; should be connected to 3.3 V at all times.
47 VSS power_in Digital ground pin.
48 GPIO51 bidirectional General-purpose I/O 51 with alternate functions EQEP1B, MDRA and TZ2.
49 GPIO9 bidirectional General-purpose I/O 9 with alternate functions EPWM5B, SCITXDB and ECAP3.
50 GPIO28 bidirectional General-purpose I/O 28 with alternate functions SCIRXDA, SDAA (open-drain I2C data) and TZ2.
51 GPIO18 bidirectional General-purpose I/O 18 with alternate functions SPICLKA, SCITXDB and XCLKOUT; XCLKOUT is SYSCLKOUT/4 at reset.
52 GPIO17 bidirectional General-purpose I/O 17 with alternate functions SPISOMIA and TZ3.
53 GPIO52 bidirectional General-purpose I/O 52 with alternate functions EQEP1S, MCLKXA and TZ3.
54 GPIO8 bidirectional General-purpose I/O 8 with alternate functions EPWM5A (HRPWM channel) and ADCSOCAO.
55 GPIO16 bidirectional General-purpose I/O 16 with alternate functions SPISIMOA and TZ2.
56 GPIO44 bidirectional General-purpose I/O 44 with alternate functions MFSRA, SCIRXDB and EPWM7B.
57 GPIO7 bidirectional General-purpose I/O 7 with alternate functions EPWM4B, SCIRXDA and ECAP2.
58 GPIO6 bidirectional General-purpose I/O 6 with alternate functions EPWM4A (HRPWM channel), EPWMSYNCI and EPWMSYNCO.
59 X2 output On-chip crystal oscillator output; a quartz crystal or ceramic resonator connects across X1 and X2, and X2 must be left unconnected if not used.
60 X1 input On-chip 1.8-V crystal oscillator input; must be tied to GND if the oscillator is not used.
61 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
62 VSS power_in Digital ground pin.
63 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF capacitor between each VDD pin and ground.
64 GPIO19 bidirectional General-purpose I/O 19 with alternate functions XCLKIN (external oscillator input, not gated by the mux), SPISTEA, SCIRXDB and ECAP1; the path to the clock block must not be enabled if the pin is used for other functions.
65 GPIO53 bidirectional General-purpose I/O 53 with alternate functions EQEP1I, MFSXA.
66 GPIO39 bidirectional General-purpose I/O 39 (no alternate function listed for this pin).
67 GPIO38 bidirectional General-purpose I/O 38 with alternate functions XCLKIN (external oscillator input, default selection) and TCK (JTAG test clock with internal pullup); must not be used as XCLKIN clock during JTAG debug.
68 GPIO34 bidirectional General-purpose I/O 34 with alternate functions COMP2OUT and COMP3OUT; this I/O may glitch during power-up when VREG is used.
69 GPIO54 bidirectional General-purpose I/O 54 with alternate functions SPISIMOA, EQEP2A (PZ/PZP only) and HRCAP1.
70 GPIO37 bidirectional General-purpose I/O 37 with alternate function TDO (JTAG scan out, 8-mA drive); TDO shifts out on the falling edge of TCK.
71 GPIO35 bidirectional General-purpose I/O 35 with alternate function TDI (JTAG test data input with internal pullup).
72 GPIO36 bidirectional General-purpose I/O 36 with alternate function TMS (JTAG test-mode select with internal pullup).
73 GPIO11 bidirectional General-purpose I/O 11 with alternate functions EPWM6B, SCIRXDB and ECAP1.
74 GPIO10 bidirectional General-purpose I/O 10 with alternate functions EPWM6A (HRPWM channel) and ADCSOCBO.
75 GPIO55 bidirectional General-purpose I/O 55 with alternate functions SPISOMIA, EQEP2B (PZ/PZP only) and HRCAP2.
76 GPIO41 bidirectional General-purpose I/O 41 with alternate functions EPWM7B and SCIRXDB.
77 GPIO27 bidirectional General-purpose I/O 27 with alternate functions HRCAP2, EQEP2S (PZ/PZP only), SPISTEB and USB0DM (USB negative differential; requires USBIOEN in GPACTRL2 on U devices).
78 GPIO26 bidirectional General-purpose I/O 26 with alternate functions ECAP3, EQEP2I (PZ/PZP only), SPICLKB and USB0DP (USB positive differential; requires USBIOEN in GPACTRL2 on U devices); may glitch during VREG power-up.
79 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
80 VSS power_in Digital ground pin.
81 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF capacitor between each VDD pin and ground.
82 GPIO40 bidirectional General-purpose I/O 40 with alternate functions EPWM7A and SCITXDB.
83 GPIO3 bidirectional General-purpose I/O 3 with alternate functions EPWM2B, SPISOMIA and COMP2OUT.
84 GPIO2 bidirectional General-purpose I/O 2 with alternate function EPWM2A (HRPWM channel).
85 GPIO56 bidirectional General-purpose I/O 56 with alternate functions SPICLKA, EQEP2I (PZ/PZP only) and HRCAP3.
86 GPIO1 bidirectional General-purpose I/O 1 with alternate functions EPWM1B and COMP1OUT.
87 GPIO0 bidirectional General-purpose I/O 0 with alternate function EPWM1A (HRPWM channel).
88 GPIO15 bidirectional General-purpose I/O 15 with alternate functions ECAP2, SCIRXDB and SPISTEB.
89 GPIO57 bidirectional General-purpose I/O 57 with alternate functions SPISTEA, EQEP2S (PZ/PZP only) and HRCAP4.
90 VREGENZ input Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG and to VDDIO to disable it and use an external 1.8-V supply.
91 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF capacitor between each VDD pin and ground.
92 VSS power_in Digital ground pin.
93 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
94 GPIO58 bidirectional General-purpose I/O 58 with alternate functions MCLKRA, SCITXDB and EPWM7A.
95 GPIO13 bidirectional General-purpose I/O 13 with alternate functions TZ2 and SPISOMIB.
96 GPIO14 bidirectional General-purpose I/O 14 with alternate functions TZ3, SCITXDB and SPICLKB.
97 GPIO24 bidirectional General-purpose I/O 24 with alternate functions ECAP1, EQEP2A (PZ/PZP only) and SPISIMOB.
98 GPIO22 bidirectional General-purpose I/O 22 with alternate functions EQEP1S, MCLKXA and SCITXDB.
99 GPIO32 bidirectional General-purpose I/O 32 with alternate functions SDAA (open-drain I2C data), EPWMSYNCI and ADCSOCAO.
100 GPIO33 bidirectional General-purpose I/O 33 with alternate functions SCLA (open-drain I2C clock), EPWMSYNCO and ADCSOCBO.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28069UPZT
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28069upzt-etched.step / tms320f28069upzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28069upzt.step / tms320f28069upzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF