component
TMS320F28069PZT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+137@@ -0,0 +1,137 @@+# TMS320F28069PZT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)++TMS320F28069PZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO42 | bidirectional | General-purpose I/O 42, alternately EPWM8A (Enhanced PWM8 output A/HRPWM channel), TZ1 (Trip Zone input 1), or COMP1OUT (direct output of Comparator 1); GPIO is default at reset. |+| 2 | GPIO23 | bidirectional | General-purpose I/O 23, alternately EQEP1I (Enhanced QEP1 index I/O), MFSXA (McBSP transmit frame synch I/O), or SCIRXDB (SCI-B receive data); GPIO is default at reset. |+| 3 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground. |+| 4 | VSS | power_in | Digital ground pin. |+| 5 | VDDIO | power_in | Digital I/O buffers power pin, single supply source when VREG is enabled; place a decoupling capacitor on each pin. |+| 6 | GPIO20 | bidirectional | General-purpose I/O 20, alternately EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data output), or COMP1OUT (direct output of Comparator 1); GPIO is default at reset. |+| 7 | GPIO21 | bidirectional | General-purpose I/O 21, alternately EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data input), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset. |+| 8 | GPIO43 | bidirectional | General-purpose I/O 43, alternately EPWM8B (Enhanced PWM8 output B), TZ2 (Trip Zone input 2), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset. |+| 9 | GPIO4 | bidirectional | General-purpose I/O 4, alternately EPWM3A (Enhanced PWM3 output A and HRPWM channel); GPIO is default at reset. |+| 10 | GPIO5 | bidirectional | General-purpose I/O 5, alternately EPWM3B (Enhanced PWM3 output B), SPISIMOA (SPI-A slave-in/master-out), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset. |+| 11 | XRS | bidirectional | Device Reset input and Watchdog Reset open-drain output with internal pullup; requires a 2.2-kOhm to 10-kOhm resistor to VDDIO (and optional <=100-nF noise-filter cap to VSS) and is driven low for 512 OSCCLK cycles during a watchdog reset. |+| 12 | TRST | input | JTAG test reset, active-high with internal pulldown; must be held low at all times during normal operation using an external pulldown resistor (~2.2 kOhm typical) or the device enters JTAG scan mode. |+| 13 | VDDIO | power_in | Digital I/O buffers power pin; place a decoupling capacitor on each pin. |+| 14 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground. |+| 15 | VSS | power_in | Digital ground pin. |+| 16 | ADCINA7 | input | ADC Group A, Channel 7 analog input. |+| 17 | ADCINA6 | bidirectional | ADC Group A Channel 6 input, alternately Comparator Input 3A (COMP3A) or Digital AIO 6 (AIO6) general-purpose I/O. |+| 18 | ADCINA5 | input | ADC Group A, Channel 5 analog input. |+| 19 | ADCINA4 | bidirectional | ADC Group A Channel 4 input, alternately Comparator Input 2A (COMP2A) or Digital AIO 4 (AIO4) general-purpose I/O. |+| 20 | ADCINA3 | input | ADC Group A, Channel 3 analog input. |+| 21 | ADCINA2 | bidirectional | ADC Group A Channel 2 input, alternately Comparator Input 1A (COMP1A) or Digital AIO 2 (AIO2) general-purpose I/O. |+| 22 | ADCINA1 | input | ADC Group A, Channel 1 analog input. |+| 23 | ADCINA0 | input | ADC Group A, Channel 0 analog input (a separate dedicated pin from VREFHI on the 100-pin PZ/PZP packages). |+| 24 | VREFHI | input | ADC external reference high input, used only in ADC external reference mode; VREFHI must not exceed VDDA. |+| 25 | VDDA | power_in | Analog power pin; tie with a 2.2-uF capacitor (typical) close to the pin. |+| 26 | VSSA | power_in | Analog ground pin. |+| 27 | VREFLO | input | ADC external reference low input, used only in ADC external reference mode. |+| 28 | ADCINB0 | input | ADC Group B, Channel 0 analog input. |+| 29 | ADCINB1 | input | ADC Group B, Channel 1 analog input. |+| 30 | ADCINB2 | bidirectional | ADC Group B Channel 2 input, alternately Comparator Input 1B (COMP1B) or Digital AIO 10 (AIO10) general-purpose I/O. |+| 31 | ADCINB3 | input | ADC Group B, Channel 3 analog input. |+| 32 | ADCINB4 | bidirectional | ADC Group B Channel 4 input, alternately Comparator Input 2B (COMP2B) or Digital AIO 12 (AIO12) general-purpose I/O. |+| 33 | ADCINB5 | input | ADC Group B, Channel 5 analog input. |+| 34 | ADCINB6 | bidirectional | ADC Group B Channel 6 input, alternately Comparator Input 3B (COMP3B) or Digital AIO 14 (AIO14) general-purpose I/O. |+| 35 | ADCINB7 | input | ADC Group B, Channel 7 analog input. |+| 36 | VSS | power_in | Digital ground pin. |+| 37 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground. |+| 38 | VDDIO | power_in | Digital I/O buffers power pin; place a decoupling capacitor on each pin. |+| 39 | GPIO25 | bidirectional | General-purpose I/O 25, alternately ECAP2 (Enhanced Capture 2 I/O), EQEP2B (Enhanced QEP2 input B, available only on PZ/PZP packages), or SPISOMIB (SPI-B slave out/master in); GPIO is default at reset. |+| 40 | GPIO31 | bidirectional | General-purpose I/O 31, alternately CANTXA (CAN transmit), EQEP2S (Enhanced QEP2 strobe, available only on PZ/PZP packages), or EPWM8A (Enhanced PWM8 output A/HRPWM channel); GPIO is default at reset. |+| 41 | GPIO30 | bidirectional | General-purpose I/O 30, alternately CANRXA (CAN receive), EQEP2I (Enhanced QEP2 index, available only on PZ/PZP packages), or EPWM7A (Enhanced PWM7 output A/HRPWM channel); GPIO is default at reset. |+| 42 | GPIO50 | bidirectional | General-purpose I/O 50, alternately EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data), or TZ1 (Trip Zone input 1); GPIO is default at reset. |+| 43 | GPIO29 | bidirectional | General-purpose I/O 29, alternately SCITXDA (SCI-A transmit data), SCLA (I2C clock open-drain bidirectional), or TZ3 (Trip Zone input 3); GPIO is default at reset. |+| 44 | GPIO12 | bidirectional | General-purpose I/O 12, alternately TZ1 (Trip Zone input 1), SCITXDA (SCI-A transmit data), or SPISIMOB (SPI-B slave-in/master-out); GPIO is default at reset. |+| 45 | TEST2 | unconnected | Test pin reserved for TI; must be left unconnected in the application. |+| 46 | VDD3VFL | power_in | 3.3-V Flash core power pin; this pin should be connected to 3.3 V at all times. |+| 47 | VSS | power_in | Digital ground pin. |+| 48 | GPIO51 | bidirectional | General-purpose I/O 51, alternately EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data), or TZ2 (Trip Zone input 2); GPIO is default at reset. |+| 49 | GPIO9 | bidirectional | General-purpose I/O 9, alternately EPWM5B (Enhanced PWM5 output B), SCITXDB (SCI-B transmit data), or ECAP3 (Enhanced Capture 3 I/O); GPIO is default at reset. |+| 50 | GPIO28 | bidirectional | General-purpose I/O 28, alternately SCIRXDA (SCI-A receive data), SDAA (I2C data open-drain bidirectional), or TZ2 (Trip Zone input 2); GPIO is default at reset. |+| 51 | GPIO18 | bidirectional | General-purpose I/O 18, alternately SPICLKA (SPI-A clock I/O), SCITXDB (SCI-B transmit data), or XCLKOUT (buffered SYSCLKOUT output, divide ratio set by XCLKOUTDIV bits, defaults to /4 at reset); GPIO is default at reset. |+| 52 | GPIO17 | bidirectional | General-purpose I/O 17, alternately SPISOMIA (SPI-A slave out/master in) or TZ3 (Trip Zone input 3); GPIO is default at reset. |+| 53 | GPIO52 | bidirectional | General-purpose I/O 52, alternately EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), or TZ3 (Trip Zone input 3); GPIO is default at reset. |+| 54 | GPIO8 | bidirectional | General-purpose I/O 8, alternately EPWM5A (Enhanced PWM5 output A/HRPWM channel) or ADCSOCAO (ADC start-of-conversion A output); GPIO is default at reset. |+| 55 | GPIO16 | bidirectional | General-purpose I/O 16, alternately SPISIMOA (SPI-A slave-in/master-out) or TZ2 (Trip Zone input 2); GPIO is default at reset. |+| 56 | GPIO44 | bidirectional | General-purpose I/O 44, alternately MFSRA (McBSP receive frame synch I/O), SCIRXDB (SCI-B receive data), or EPWM7B (Enhanced PWM7 output B); GPIO is default at reset. |+| 57 | GPIO7 | bidirectional | General-purpose I/O 7, alternately EPWM4B (Enhanced PWM4 output B), SCIRXDA (SCI-A receive data), or ECAP2 (Enhanced Capture 2 I/O); GPIO is default at reset. |+| 58 | GPIO6 | bidirectional | General-purpose I/O 6, alternately EPWM4A (Enhanced PWM4 output A/HRPWM channel), EPWMSYNCI (external ePWM sync input), or EPWMSYNCO (external ePWM sync output); GPIO is default at reset. |+| 59 | X2 | output | On-chip crystal-oscillator output; a quartz crystal or ceramic resonator must be connected across X1 and X2, and X2 must be left unconnected if not used. |+| 60 | X1 | input | On-chip 1.8-V crystal-oscillator input; a quartz crystal or ceramic resonator must be connected across X1/X2 (with XCLKIN path disabled), or X1 must be tied to GND if not used. |+| 61 | VDDIO | power_in | Digital I/O buffers power pin; place a decoupling capacitor on each pin. |+| 62 | VSS | power_in | Digital ground pin. |+| 63 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground. |+| 64 | GPIO19 | bidirectional | General-purpose I/O 19, alternately XCLKIN (external oscillator input, path not mux-gated), SPISTEA (SPI-A slave transmit enable I/O), SCIRXDB (SCI-B receive data), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset. |+| 65 | GPIO53 | bidirectional | General-purpose I/O 53, alternately EQEP1I (Enhanced QEP1 index I/O) or MFSXA (McBSP transmit frame synch I/O); GPIO is default at reset. |+| 66 | GPIO39 | bidirectional | General-purpose I/O 39 with no other listed alternate peripheral function; GPIO is default at reset. |+| 67 | GPIO38 | bidirectional | General-purpose I/O 38, alternately XCLKIN (external oscillator input) or TCK (JTAG test clock with internal pullup); GPIO is default at reset. |+| 68 | GPIO34 | bidirectional | General-purpose I/O 34, alternately COMP2OUT (direct output of Comparator 2) or COMP3OUT (direct output of Comparator 3); GPIO is default at reset. |+| 69 | GPIO54 | bidirectional | General-purpose I/O 54, alternately SPISIMOA (SPI-A slave-in/master-out), EQEP2A (Enhanced QEP2 input A), or HRCAP1 (High-Resolution Input Capture 1); GPIO is default at reset. |+| 70 | GPIO37 | bidirectional | General-purpose I/O 37, alternately TDO (JTAG test data output, 8-mA drive, shifted out on the falling edge of TCK); GPIO is default at reset. |+| 71 | GPIO35 | bidirectional | General-purpose I/O 35, alternately TDI (JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK); GPIO is default at reset. |+| 72 | GPIO36 | bidirectional | General-purpose I/O 36, alternately TMS (JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK); GPIO is default at reset. |+| 73 | GPIO11 | bidirectional | General-purpose I/O 11, alternately EPWM6B (Enhanced PWM6 output B), SCIRXDB (SCI-B receive data), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset. |+| 74 | GPIO10 | bidirectional | General-purpose I/O 10, alternately EPWM6A (Enhanced PWM6 output A/HRPWM channel) or ADCSOCBO (ADC start-of-conversion B output); GPIO is default at reset. |+| 75 | GPIO55 | bidirectional | General-purpose I/O 55, alternately SPISOMIA (SPI-A slave out/master in), EQEP2B (Enhanced QEP2 input B), or HRCAP2 (High-Resolution Input Capture 2); GPIO is default at reset. |+| 76 | GPIO41 | bidirectional | General-purpose I/O 41, alternately EPWM7B (Enhanced PWM7 output B) or SCIRXDB (SCI-B receive data); GPIO is default at reset. |+| 77 | GPIO27 | bidirectional | General-purpose I/O 27, alternately HRCAP2 (High-Resolution Input Capture 2), EQEP2S (Enhanced QEP2 strobe), SPISTEB (SPI-B slave transmit enable I/O), or USB0DM (USB negative differential signal, enabled via the USBIOEN bit in GPACTRL2); GPIO is default at reset. |+| 78 | GPIO26 | bidirectional | General-purpose I/O 26, alternately ECAP3 (Enhanced Capture 3 I/O), EQEP2I (Enhanced QEP2 index), SPICLKB (SPI-B clock I/O), or USB0DP (USB positive differential signal, enabled via the USBIOEN bit in GPACTRL2); GPIO is default at reset. |+| 79 | VDDIO | power_in | Digital I/O buffers power pin; place a decoupling capacitor on each pin. |+| 80 | VSS | power_in | Digital ground pin. |+| 81 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground. |+| 82 | GPIO40 | bidirectional | General-purpose I/O 40, alternately EPWM7A (Enhanced PWM7 output A/HRPWM channel) or SCITXDB (SCI-B transmit data); GPIO is default at reset. |+| 83 | GPIO3 | bidirectional | General-purpose I/O 3, alternately EPWM2B (Enhanced PWM2 output B), SPISOMIA (SPI-A slave out/master in), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset. |+| 84 | GPIO2 | bidirectional | General-purpose I/O 2, alternately EPWM2A (Enhanced PWM2 output A/HRPWM channel); GPIO is default at reset. |+| 85 | GPIO56 | bidirectional | General-purpose I/O 56, alternately SPICLKA (SPI-A clock I/O), EQEP2I (Enhanced QEP2 index I/O), or HRCAP3 (High-Resolution Input Capture 3); GPIO is default at reset. |+| 86 | GPIO1 | bidirectional | General-purpose I/O 1, alternately EPWM1B (Enhanced PWM1 output B) or COMP1OUT (direct output of Comparator 1); GPIO is default at reset. |+| 87 | GPIO0 | bidirectional | General-purpose I/O 0, alternately EPWM1A (Enhanced PWM1 output A/HRPWM channel); GPIO is default at reset. |+| 88 | GPIO15 | bidirectional | General-purpose I/O 15, alternately ECAP2 (Enhanced Capture 2 I/O), SCIRXDB (SCI-B receive data), or SPISTEB (SPI-B slave transmit enable I/O); GPIO is default at reset. |+| 89 | GPIO57 | bidirectional | General-purpose I/O 57, alternately SPISTEA (SPI-A slave transmit enable I/O), EQEP2S (Enhanced QEP2 strobe I/O), or HRCAP4 (High-Resolution Input Capture 4); GPIO is default at reset. |+| 90 | VREGENZ | input | Internal voltage regulator (VREG) enable with internal pulldown; tie directly to VSS to enable the internal 1.8-V VREG, or tie directly to VDDIO to disable the VREG and use an external 1.8-V supply. |+| 91 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground. |+| 92 | VSS | power_in | Digital ground pin. |+| 93 | VDDIO | power_in | Digital I/O buffers power pin; place a decoupling capacitor on each pin. |+| 94 | GPIO58 | bidirectional | General-purpose I/O 58, alternately MCLKRA (McBSP receive clock I/O), SCITXDB (SCI-B transmit data), or EPWM7A (Enhanced PWM7 output A/HRPWM channel); GPIO is default at reset. |+| 95 | GPIO13 | bidirectional | General-purpose I/O 13, alternately TZ2 (Trip Zone input 2) or SPISOMIB (SPI-B slave out/master in); GPIO is default at reset. |+| 96 | GPIO14 | bidirectional | General-purpose I/O 14, alternately TZ3 (Trip Zone input 3), SCITXDB (SCI-B transmit data), or SPICLKB (SPI-B clock I/O); GPIO is default at reset. |+| 97 | GPIO24 | bidirectional | General-purpose I/O 24, alternately ECAP1 (Enhanced Capture 1 I/O), EQEP2A (Enhanced QEP2 input A, available only on PZ/PZP packages), or SPISIMOB (SPI-B slave-in/master-out); GPIO is default at reset. |+| 98 | GPIO22 | bidirectional | General-purpose I/O 22, alternately EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), or SCITXDB (SCI-B transmit data); GPIO is default at reset. |+| 99 | GPIO32 | bidirectional | General-purpose I/O 32, alternately SDAA (I2C data open-drain bidirectional), EPWMSYNCI (Enhanced PWM external sync pulse input), or ADCSOCAO (ADC start-of-conversion A output); GPIO is default at reset. |+| 100 | GPIO33 | bidirectional | General-purpose I/O 33, alternately SCLA (I2C clock open-drain bidirectional), EPWMSYNCO (Enhanced PWM external sync pulse output), or ADCSOCBO (ADC start-of-conversion B output); GPIO is default at reset. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-100(14x14) |+| Category | Embedded Processors & Controllers |+| Pins | 100 |++## CAD (KiCad official)++- Symbol: `TMS320F28069PZT`+- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`+- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)+- 3D model files: `tms320f28069pzt-etched.step` / `tms320f28069pzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28069pzt.step` / `tms320f28069pzt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28069) (206 pp, sha256 `3033efed856fc72a`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28069pzt-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28069pzt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28069pzt.kicad_sym",+ "tms320f28069pzt.kicad_mod",+ "tms320f28069pzt.glb",+ "tms320f28069pzt.step",+ "tms320f28069pzt.lbr",+ "docs/hero.png",+ "docs/tms320f28069pzt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TMS320F28069PZT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-100(14x14)",+ "pin_count": 100,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28069",+ "parts": {+ "symbol": "tms320f28069pzt.kicad_sym",+ "footprint": "tms320f28069pzt.kicad_mod",+ "model_3d": "tms320f28069pzt-etched.glb",+ "model_3d_plain": "tms320f28069pzt.glb",+ "model_3d_step": "tms320f28069pzt-etched.step",+ "model_3d_step_plain": "tms320f28069pzt.step",+ "lbr": "tms320f28069pzt.lbr"+ },+ "distributor_links": {+ "lcsc": "C82775"+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO42",+ "type": "bidirectional",+ "description": "General-purpose I/O 42, alternately EPWM8A (Enhanced PWM8 output A/HRPWM channel), TZ1 (Trip Zone input 1), or COMP1OUT (direct output of Comparator 1); GPIO is default at reset."+ },+ {+ "number": "2",+ "name": "GPIO23",+ "type": "bidirectional",+ "description": "General-purpose I/O 23, alternately EQEP1I (Enhanced QEP1 index I/O), MFSXA (McBSP transmit frame synch I/O), or SCIRXDB (SCI-B receive data); GPIO is default at reset."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground."+ },+ {+ "number": "4",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "5",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffers power pin, single supply source when VREG is enabled; place a decoupling capacitor on each pin."+ },+ {+ "number": "6",+ "name": "GPIO20",+ "type": "bidirectional",+ "description": "General-purpose I/O 20, alternately EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data output), or COMP1OUT (direct output of Comparator 1); GPIO is default at reset."+ },+ {+ "number": "7",+ "name": "GPIO21",+ "type": "bidirectional",+ "description": "General-purpose I/O 21, alternately EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data input), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset."+ },+ {+ "number": "8",+ "name": "GPIO43",+ "type": "bidirectional",+ "description": "General-purpose I/O 43, alternately EPWM8B (Enhanced PWM8 output B), TZ2 (Trip Zone input 2), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset."+ },+ {+ "number": "9",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O 4, alternately EPWM3A (Enhanced PWM3 output A and HRPWM channel); GPIO is default at reset."+ },+ {+ "number": "10",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O 5, alternately EPWM3B (Enhanced PWM3 output B), SPISIMOA (SPI-A slave-in/master-out), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset."+ },+ {+ "number": "11",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Device Reset input and Watchdog Reset open-drain output with internal pullup; requires a 2.2-kOhm to 10-kOhm resistor to VDDIO (and optional <=100-nF noise-filter cap to VSS) and is driven low for 512 OSCCLK cycles during a watchdog reset."+ },+ {+ "number": "12",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset, active-high with internal pulldown; must be held low at all times during normal operation using an external pulldown resistor (~2.2 kOhm typical) or the device enters JTAG scan mode."+ },+ {+ "number": "13",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffers power pin; place a decoupling capacitor on each pin."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground."+ },+ {+ "number": "15",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "16",+ "name": "ADCINA7",+ "type": "input",+ "description": "ADC Group A, Channel 7 analog input."+ },+ {+ "number": "17",+ "name": "ADCINA6",+ "type": "bidirectional",+ "description": "ADC Group A Channel 6 input, alternately Comparator Input 3A (COMP3A) or Digital AIO 6 (AIO6) general-purpose I/O."+ },+ {+ "number": "18",+ "name": "ADCINA5",+ "type": "input",+ "description": "ADC Group A, Channel 5 analog input."+ },+ {+ "number": "19",+ "name": "ADCINA4",+ "type": "bidirectional",+ "description": "ADC Group A Channel 4 input, alternately Comparator Input 2A (COMP2A) or Digital AIO 4 (AIO4) general-purpose I/O."+ },+ {+ "number": "20",+ "name": "ADCINA3",+ "type": "input",+ "description": "ADC Group A, Channel 3 analog input."+ },+ {+ "number": "21",+ "name": "ADCINA2",+ "type": "bidirectional",+ "description": "ADC Group A Channel 2 input, alternately Comparator Input 1A (COMP1A) or Digital AIO 2 (AIO2) general-purpose I/O."+ },+ {+ "number": "22",+ "name": "ADCINA1",+ "type": "input",+ "description": "ADC Group A, Channel 1 analog input."+ },+ {+ "number": "23",+ "name": "ADCINA0",+ "type": "input",+ "description": "ADC Group A, Channel 0 analog input (a separate dedicated pin from VREFHI on the 100-pin PZ/PZP packages)."+ },+ {+ "number": "24",+ "name": "VREFHI",+ "type": "input",+ "description": "ADC external reference high input, used only in ADC external reference mode; VREFHI must not exceed VDDA."+ },+ {+ "number": "25",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power pin; tie with a 2.2-uF capacitor (typical) close to the pin."+ },+ {+ "number": "26",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "27",+ "name": "VREFLO",+ "type": "input",+ "description": "ADC external reference low input, used only in ADC external reference mode."+ },+ {+ "number": "28",+ "name": "ADCINB0",+ "type": "input",+ "description": "ADC Group B, Channel 0 analog input."+ },+ {+ "number": "29",+ "name": "ADCINB1",+ "type": "input",+ "description": "ADC Group B, Channel 1 analog input."+ },+ {+ "number": "30",+ "name": "ADCINB2",+ "type": "bidirectional",+ "description": "ADC Group B Channel 2 input, alternately Comparator Input 1B (COMP1B) or Digital AIO 10 (AIO10) general-purpose I/O."+ },+ {+ "number": "31",+ "name": "ADCINB3",+ "type": "input",+ "description": "ADC Group B, Channel 3 analog input."+ },+ {+ "number": "32",+ "name": "ADCINB4",+ "type": "bidirectional",+ "description": "ADC Group B Channel 4 input, alternately Comparator Input 2B (COMP2B) or Digital AIO 12 (AIO12) general-purpose I/O."+ },+ {+ "number": "33",+ "name": "ADCINB5",+ "type": "input",+ "description": "ADC Group B, Channel 5 analog input."+ },+ {+ "number": "34",+ "name": "ADCINB6",+ "type": "bidirectional",+ "description": "ADC Group B Channel 6 input, alternately Comparator Input 3B (COMP3B) or Digital AIO 14 (AIO14) general-purpose I/O."+ },+ {+ "number": "35",+ "name": "ADCINB7",+ "type": "input",+ "description": "ADC Group B, Channel 7 analog input."+ },+ {+ "number": "36",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "37",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground."+ },+ {+ "number": "38",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffers power pin; place a decoupling capacitor on each pin."+ },+ {+ "number": "39",+ "name": "GPIO25",+ "type": "bidirectional",+ "description": "General-purpose I/O 25, alternately ECAP2 (Enhanced Capture 2 I/O), EQEP2B (Enhanced QEP2 input B, available only on PZ/PZP packages), or SPISOMIB (SPI-B slave out/master in); GPIO is default at reset."+ },+ {+ "number": "40",+ "name": "GPIO31",+ "type": "bidirectional",+ "description": "General-purpose I/O 31, alternately CANTXA (CAN transmit), EQEP2S (Enhanced QEP2 strobe, available only on PZ/PZP packages), or EPWM8A (Enhanced PWM8 output A/HRPWM channel); GPIO is default at reset."+ },+ {+ "number": "41",+ "name": "GPIO30",+ "type": "bidirectional",+ "description": "General-purpose I/O 30, alternately CANRXA (CAN receive), EQEP2I (Enhanced QEP2 index, available only on PZ/PZP packages), or EPWM7A (Enhanced PWM7 output A/HRPWM channel); GPIO is default at reset."+ },+ {+ "number": "42",+ "name": "GPIO50",+ "type": "bidirectional",+ "description": "General-purpose I/O 50, alternately EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data), or TZ1 (Trip Zone input 1); GPIO is default at reset."+ },+ {+ "number": "43",+ "name": "GPIO29",+ "type": "bidirectional",+ "description": "General-purpose I/O 29, alternately SCITXDA (SCI-A transmit data), SCLA (I2C clock open-drain bidirectional), or TZ3 (Trip Zone input 3); GPIO is default at reset."+ },+ {+ "number": "44",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O 12, alternately TZ1 (Trip Zone input 1), SCITXDA (SCI-A transmit data), or SPISIMOB (SPI-B slave-in/master-out); GPIO is default at reset."+ },+ {+ "number": "45",+ "name": "TEST2",+ "type": "unconnected",+ "description": "Test pin reserved for TI; must be left unconnected in the application."+ },+ {+ "number": "46",+ "name": "VDD3VFL",+ "type": "power_in",+ "description": "3.3-V Flash core power pin; this pin should be connected to 3.3 V at all times."+ },+ {+ "number": "47",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "48",+ "name": "GPIO51",+ "type": "bidirectional",+ "description": "General-purpose I/O 51, alternately EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data), or TZ2 (Trip Zone input 2); GPIO is default at reset."+ },+ {+ "number": "49",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O 9, alternately EPWM5B (Enhanced PWM5 output B), SCITXDB (SCI-B transmit data), or ECAP3 (Enhanced Capture 3 I/O); GPIO is default at reset."+ },+ {+ "number": "50",+ "name": "GPIO28",+ "type": "bidirectional",+ "description": "General-purpose I/O 28, alternately SCIRXDA (SCI-A receive data), SDAA (I2C data open-drain bidirectional), or TZ2 (Trip Zone input 2); GPIO is default at reset."+ },+ {+ "number": "51",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose I/O 18, alternately SPICLKA (SPI-A clock I/O), SCITXDB (SCI-B transmit data), or XCLKOUT (buffered SYSCLKOUT output, divide ratio set by XCLKOUTDIV bits, defaults to /4 at reset); GPIO is default at reset."+ },+ {+ "number": "52",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O 17, alternately SPISOMIA (SPI-A slave out/master in) or TZ3 (Trip Zone input 3); GPIO is default at reset."+ },+ {+ "number": "53",+ "name": "GPIO52",+ "type": "bidirectional",+ "description": "General-purpose I/O 52, alternately EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), or TZ3 (Trip Zone input 3); GPIO is default at reset."+ },+ {+ "number": "54",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O 8, alternately EPWM5A (Enhanced PWM5 output A/HRPWM channel) or ADCSOCAO (ADC start-of-conversion A output); GPIO is default at reset."+ },+ {+ "number": "55",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "General-purpose I/O 16, alternately SPISIMOA (SPI-A slave-in/master-out) or TZ2 (Trip Zone input 2); GPIO is default at reset."+ },+ {+ "number": "56",+ "name": "GPIO44",+ "type": "bidirectional",+ "description": "General-purpose I/O 44, alternately MFSRA (McBSP receive frame synch I/O), SCIRXDB (SCI-B receive data), or EPWM7B (Enhanced PWM7 output B); GPIO is default at reset."+ },+ {+ "number": "57",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O 7, alternately EPWM4B (Enhanced PWM4 output B), SCIRXDA (SCI-A receive data), or ECAP2 (Enhanced Capture 2 I/O); GPIO is default at reset."+ },+ {+ "number": "58",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O 6, alternately EPWM4A (Enhanced PWM4 output A/HRPWM channel), EPWMSYNCI (external ePWM sync input), or EPWMSYNCO (external ePWM sync output); GPIO is default at reset."+ },+ {+ "number": "59",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal-oscillator output; a quartz crystal or ceramic resonator must be connected across X1 and X2, and X2 must be left unconnected if not used."+ },+ {+ "number": "60",+ "name": "X1",+ "type": "input",+ "description": "On-chip 1.8-V crystal-oscillator input; a quartz crystal or ceramic resonator must be connected across X1/X2 (with XCLKIN path disabled), or X1 must be tied to GND if not used."+ },+ {+ "number": "61",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffers power pin; place a decoupling capacitor on each pin."+ },+ {+ "number": "62",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "63",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground."+ },+ {+ "number": "64",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O 19, alternately XCLKIN (external oscillator input, path not mux-gated), SPISTEA (SPI-A slave transmit enable I/O), SCIRXDB (SCI-B receive data), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset."+ },+ {+ "number": "65",+ "name": "GPIO53",+ "type": "bidirectional",+ "description": "General-purpose I/O 53, alternately EQEP1I (Enhanced QEP1 index I/O) or MFSXA (McBSP transmit frame synch I/O); GPIO is default at reset."+ },+ {+ "number": "66",+ "name": "GPIO39",+ "type": "bidirectional",+ "description": "General-purpose I/O 39 with no other listed alternate peripheral function; GPIO is default at reset."+ },+ {+ "number": "67",+ "name": "GPIO38",+ "type": "bidirectional",+ "description": "General-purpose I/O 38, alternately XCLKIN (external oscillator input) or TCK (JTAG test clock with internal pullup); GPIO is default at reset."+ },+ {+ "number": "68",+ "name": "GPIO34",+ "type": "bidirectional",+ "description": "General-purpose I/O 34, alternately COMP2OUT (direct output of Comparator 2) or COMP3OUT (direct output of Comparator 3); GPIO is default at reset."+ },+ {+ "number": "69",+ "name": "GPIO54",+ "type": "bidirectional",+ "description": "General-purpose I/O 54, alternately SPISIMOA (SPI-A slave-in/master-out), EQEP2A (Enhanced QEP2 input A), or HRCAP1 (High-Resolution Input Capture 1); GPIO is default at reset."+ },+ {+ "number": "70",+ "name": "GPIO37",+ "type": "bidirectional",+ "description": "General-purpose I/O 37, alternately TDO (JTAG test data output, 8-mA drive, shifted out on the falling edge of TCK); GPIO is default at reset."+ },+ {+ "number": "71",+ "name": "GPIO35",+ "type": "bidirectional",+ "description": "General-purpose I/O 35, alternately TDI (JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK); GPIO is default at reset."+ },+ {+ "number": "72",+ "name": "GPIO36",+ "type": "bidirectional",+ "description": "General-purpose I/O 36, alternately TMS (JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK); GPIO is default at reset."+ },+ {+ "number": "73",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O 11, alternately EPWM6B (Enhanced PWM6 output B), SCIRXDB (SCI-B receive data), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset."+ },+ {+ "number": "74",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O 10, alternately EPWM6A (Enhanced PWM6 output A/HRPWM channel) or ADCSOCBO (ADC start-of-conversion B output); GPIO is default at reset."+ },+ {+ "number": "75",+ "name": "GPIO55",+ "type": "bidirectional",+ "description": "General-purpose I/O 55, alternately SPISOMIA (SPI-A slave out/master in), EQEP2B (Enhanced QEP2 input B), or HRCAP2 (High-Resolution Input Capture 2); GPIO is default at reset."+ },+ {+ "number": "76",+ "name": "GPIO41",+ "type": "bidirectional",+ "description": "General-purpose I/O 41, alternately EPWM7B (Enhanced PWM7 output B) or SCIRXDB (SCI-B receive data); GPIO is default at reset."+ },+ {+ "number": "77",+ "name": "GPIO27",+ "type": "bidirectional",+ "description": "General-purpose I/O 27, alternately HRCAP2 (High-Resolution Input Capture 2), EQEP2S (Enhanced QEP2 strobe), SPISTEB (SPI-B slave transmit enable I/O), or USB0DM (USB negative differential signal, enabled via the USBIOEN bit in GPACTRL2); GPIO is default at reset."+ },+ {+ "number": "78",+ "name": "GPIO26",+ "type": "bidirectional",+ "description": "General-purpose I/O 26, alternately ECAP3 (Enhanced Capture 3 I/O), EQEP2I (Enhanced QEP2 index), SPICLKB (SPI-B clock I/O), or USB0DP (USB positive differential signal, enabled via the USBIOEN bit in GPACTRL2); GPIO is default at reset."+ },+ {+ "number": "79",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffers power pin; place a decoupling capacitor on each pin."+ },+ {+ "number": "80",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "81",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground."+ },+ {+ "number": "82",+ "name": "GPIO40",+ "type": "bidirectional",+ "description": "General-purpose I/O 40, alternately EPWM7A (Enhanced PWM7 output A/HRPWM channel) or SCITXDB (SCI-B transmit data); GPIO is default at reset."+ },+ {+ "number": "83",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O 3, alternately EPWM2B (Enhanced PWM2 output B), SPISOMIA (SPI-A slave out/master in), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset."+ },+ {+ "number": "84",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O 2, alternately EPWM2A (Enhanced PWM2 output A/HRPWM channel); GPIO is default at reset."+ },+ {+ "number": "85",+ "name": "GPIO56",+ "type": "bidirectional",+ "description": "General-purpose I/O 56, alternately SPICLKA (SPI-A clock I/O), EQEP2I (Enhanced QEP2 index I/O), or HRCAP3 (High-Resolution Input Capture 3); GPIO is default at reset."+ },+ {+ "number": "86",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O 1, alternately EPWM1B (Enhanced PWM1 output B) or COMP1OUT (direct output of Comparator 1); GPIO is default at reset."+ },+ {+ "number": "87",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O 0, alternately EPWM1A (Enhanced PWM1 output A/HRPWM channel); GPIO is default at reset."+ },+ {+ "number": "88",+ "name": "GPIO15",+ "type": "bidirectional",+ "description": "General-purpose I/O 15, alternately ECAP2 (Enhanced Capture 2 I/O), SCIRXDB (SCI-B receive data), or SPISTEB (SPI-B slave transmit enable I/O); GPIO is default at reset."+ },+ {+ "number": "89",+ "name": "GPIO57",+ "type": "bidirectional",+ "description": "General-purpose I/O 57, alternately SPISTEA (SPI-A slave transmit enable I/O), EQEP2S (Enhanced QEP2 strobe I/O), or HRCAP4 (High-Resolution Input Capture 4); GPIO is default at reset."+ },+ {+ "number": "90",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator (VREG) enable with internal pulldown; tie directly to VSS to enable the internal 1.8-V VREG, or tie directly to VDDIO to disable the VREG and use an external 1.8-V supply."+ },+ {+ "number": "91",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground."+ },+ {+ "number": "92",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "93",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffers power pin; place a decoupling capacitor on each pin."+ },+ {+ "number": "94",+ "name": "GPIO58",+ "type": "bidirectional",+ "description": "General-purpose I/O 58, alternately MCLKRA (McBSP receive clock I/O), SCITXDB (SCI-B transmit data), or EPWM7A (Enhanced PWM7 output A/HRPWM channel); GPIO is default at reset."+ },+ {+ "number": "95",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O 13, alternately TZ2 (Trip Zone input 2) or SPISOMIB (SPI-B slave out/master in); GPIO is default at reset."+ },+ {+ "number": "96",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O 14, alternately TZ3 (Trip Zone input 3), SCITXDB (SCI-B transmit data), or SPICLKB (SPI-B clock I/O); GPIO is default at reset."+ },+ {+ "number": "97",+ "name": "GPIO24",+ "type": "bidirectional",+ "description": "General-purpose I/O 24, alternately ECAP1 (Enhanced Capture 1 I/O), EQEP2A (Enhanced QEP2 input A, available only on PZ/PZP packages), or SPISIMOB (SPI-B slave-in/master-out); GPIO is default at reset."+ },+ {+ "number": "98",+ "name": "GPIO22",+ "type": "bidirectional",+ "description": "General-purpose I/O 22, alternately EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), or SCITXDB (SCI-B transmit data); GPIO is default at reset."+ },+ {+ "number": "99",+ "name": "GPIO32",+ "type": "bidirectional",+ "description": "General-purpose I/O 32, alternately SDAA (I2C data open-drain bidirectional), EPWMSYNCI (Enhanced PWM external sync pulse input), or ADCSOCAO (ADC start-of-conversion A output); GPIO is default at reset."+ },+ {+ "number": "100",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O 33, alternately SCLA (I2C clock open-drain bidirectional), EPWMSYNCO (Enhanced PWM external sync pulse output), or ADCSOCBO (ADC start-of-conversion B output); GPIO is default at reset."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins 83-84 assignments uncertain: Based on signal descriptions table, pins 83-84 appear to be assign; GPIO pins with high-impedance/tri-state outputs: GPIO37 (pin 70) and TDO function are tri-state outp; Multiple power supply pins: Verify proper decoupling capacitor placement for VDD (pins 3,14,37,63,81",+ "2/100 pins cited to the wrong page (name found elsewhere): ['83:VSSA@p20', '84:VREFLO@p20']"+ ],+ "pages_sent": 42,+ "cost_usd": 0.9998,+ "at": "2026-09-23T10:02:11"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28069",+ "pages": 206,+ "sha256": "3033efed856fc72a",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 100,+ "described": 100,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}