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TMS320F28069PZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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TMS320F28069PZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F28069PZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO42 bidirectional General-purpose I/O 42, alternately EPWM8A (Enhanced PWM8 output A/HRPWM channel), TZ1 (Trip Zone input 1), or COMP1OUT (direct output of Comparator 1); GPIO is default at reset.
2 GPIO23 bidirectional General-purpose I/O 23, alternately EQEP1I (Enhanced QEP1 index I/O), MFSXA (McBSP transmit frame synch I/O), or SCIRXDB (SCI-B receive data); GPIO is default at reset.
3 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground.
4 VSS power_in Digital ground pin.
5 VDDIO power_in Digital I/O buffers power pin, single supply source when VREG is enabled; place a decoupling capacitor on each pin.
6 GPIO20 bidirectional General-purpose I/O 20, alternately EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data output), or COMP1OUT (direct output of Comparator 1); GPIO is default at reset.
7 GPIO21 bidirectional General-purpose I/O 21, alternately EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data input), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset.
8 GPIO43 bidirectional General-purpose I/O 43, alternately EPWM8B (Enhanced PWM8 output B), TZ2 (Trip Zone input 2), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset.
9 GPIO4 bidirectional General-purpose I/O 4, alternately EPWM3A (Enhanced PWM3 output A and HRPWM channel); GPIO is default at reset.
10 GPIO5 bidirectional General-purpose I/O 5, alternately EPWM3B (Enhanced PWM3 output B), SPISIMOA (SPI-A slave-in/master-out), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset.
11 XRS bidirectional Device Reset input and Watchdog Reset open-drain output with internal pullup; requires a 2.2-kOhm to 10-kOhm resistor to VDDIO (and optional <=100-nF noise-filter cap to VSS) and is driven low for 512 OSCCLK cycles during a watchdog reset.
12 TRST input JTAG test reset, active-high with internal pulldown; must be held low at all times during normal operation using an external pulldown resistor (~2.2 kOhm typical) or the device enters JTAG scan mode.
13 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
14 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground.
15 VSS power_in Digital ground pin.
16 ADCINA7 input ADC Group A, Channel 7 analog input.
17 ADCINA6 bidirectional ADC Group A Channel 6 input, alternately Comparator Input 3A (COMP3A) or Digital AIO 6 (AIO6) general-purpose I/O.
18 ADCINA5 input ADC Group A, Channel 5 analog input.
19 ADCINA4 bidirectional ADC Group A Channel 4 input, alternately Comparator Input 2A (COMP2A) or Digital AIO 4 (AIO4) general-purpose I/O.
20 ADCINA3 input ADC Group A, Channel 3 analog input.
21 ADCINA2 bidirectional ADC Group A Channel 2 input, alternately Comparator Input 1A (COMP1A) or Digital AIO 2 (AIO2) general-purpose I/O.
22 ADCINA1 input ADC Group A, Channel 1 analog input.
23 ADCINA0 input ADC Group A, Channel 0 analog input (a separate dedicated pin from VREFHI on the 100-pin PZ/PZP packages).
24 VREFHI input ADC external reference high input, used only in ADC external reference mode; VREFHI must not exceed VDDA.
25 VDDA power_in Analog power pin; tie with a 2.2-uF capacitor (typical) close to the pin.
26 VSSA power_in Analog ground pin.
27 VREFLO input ADC external reference low input, used only in ADC external reference mode.
28 ADCINB0 input ADC Group B, Channel 0 analog input.
29 ADCINB1 input ADC Group B, Channel 1 analog input.
30 ADCINB2 bidirectional ADC Group B Channel 2 input, alternately Comparator Input 1B (COMP1B) or Digital AIO 10 (AIO10) general-purpose I/O.
31 ADCINB3 input ADC Group B, Channel 3 analog input.
32 ADCINB4 bidirectional ADC Group B Channel 4 input, alternately Comparator Input 2B (COMP2B) or Digital AIO 12 (AIO12) general-purpose I/O.
33 ADCINB5 input ADC Group B, Channel 5 analog input.
34 ADCINB6 bidirectional ADC Group B Channel 6 input, alternately Comparator Input 3B (COMP3B) or Digital AIO 14 (AIO14) general-purpose I/O.
35 ADCINB7 input ADC Group B, Channel 7 analog input.
36 VSS power_in Digital ground pin.
37 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground.
38 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
39 GPIO25 bidirectional General-purpose I/O 25, alternately ECAP2 (Enhanced Capture 2 I/O), EQEP2B (Enhanced QEP2 input B, available only on PZ/PZP packages), or SPISOMIB (SPI-B slave out/master in); GPIO is default at reset.
40 GPIO31 bidirectional General-purpose I/O 31, alternately CANTXA (CAN transmit), EQEP2S (Enhanced QEP2 strobe, available only on PZ/PZP packages), or EPWM8A (Enhanced PWM8 output A/HRPWM channel); GPIO is default at reset.
41 GPIO30 bidirectional General-purpose I/O 30, alternately CANRXA (CAN receive), EQEP2I (Enhanced QEP2 index, available only on PZ/PZP packages), or EPWM7A (Enhanced PWM7 output A/HRPWM channel); GPIO is default at reset.
42 GPIO50 bidirectional General-purpose I/O 50, alternately EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data), or TZ1 (Trip Zone input 1); GPIO is default at reset.
43 GPIO29 bidirectional General-purpose I/O 29, alternately SCITXDA (SCI-A transmit data), SCLA (I2C clock open-drain bidirectional), or TZ3 (Trip Zone input 3); GPIO is default at reset.
44 GPIO12 bidirectional General-purpose I/O 12, alternately TZ1 (Trip Zone input 1), SCITXDA (SCI-A transmit data), or SPISIMOB (SPI-B slave-in/master-out); GPIO is default at reset.
45 TEST2 unconnected Test pin reserved for TI; must be left unconnected in the application.
46 VDD3VFL power_in 3.3-V Flash core power pin; this pin should be connected to 3.3 V at all times.
47 VSS power_in Digital ground pin.
48 GPIO51 bidirectional General-purpose I/O 51, alternately EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data), or TZ2 (Trip Zone input 2); GPIO is default at reset.
49 GPIO9 bidirectional General-purpose I/O 9, alternately EPWM5B (Enhanced PWM5 output B), SCITXDB (SCI-B transmit data), or ECAP3 (Enhanced Capture 3 I/O); GPIO is default at reset.
50 GPIO28 bidirectional General-purpose I/O 28, alternately SCIRXDA (SCI-A receive data), SDAA (I2C data open-drain bidirectional), or TZ2 (Trip Zone input 2); GPIO is default at reset.
51 GPIO18 bidirectional General-purpose I/O 18, alternately SPICLKA (SPI-A clock I/O), SCITXDB (SCI-B transmit data), or XCLKOUT (buffered SYSCLKOUT output, divide ratio set by XCLKOUTDIV bits, defaults to /4 at reset); GPIO is default at reset.
52 GPIO17 bidirectional General-purpose I/O 17, alternately SPISOMIA (SPI-A slave out/master in) or TZ3 (Trip Zone input 3); GPIO is default at reset.
53 GPIO52 bidirectional General-purpose I/O 52, alternately EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), or TZ3 (Trip Zone input 3); GPIO is default at reset.
54 GPIO8 bidirectional General-purpose I/O 8, alternately EPWM5A (Enhanced PWM5 output A/HRPWM channel) or ADCSOCAO (ADC start-of-conversion A output); GPIO is default at reset.
55 GPIO16 bidirectional General-purpose I/O 16, alternately SPISIMOA (SPI-A slave-in/master-out) or TZ2 (Trip Zone input 2); GPIO is default at reset.
56 GPIO44 bidirectional General-purpose I/O 44, alternately MFSRA (McBSP receive frame synch I/O), SCIRXDB (SCI-B receive data), or EPWM7B (Enhanced PWM7 output B); GPIO is default at reset.
57 GPIO7 bidirectional General-purpose I/O 7, alternately EPWM4B (Enhanced PWM4 output B), SCIRXDA (SCI-A receive data), or ECAP2 (Enhanced Capture 2 I/O); GPIO is default at reset.
58 GPIO6 bidirectional General-purpose I/O 6, alternately EPWM4A (Enhanced PWM4 output A/HRPWM channel), EPWMSYNCI (external ePWM sync input), or EPWMSYNCO (external ePWM sync output); GPIO is default at reset.
59 X2 output On-chip crystal-oscillator output; a quartz crystal or ceramic resonator must be connected across X1 and X2, and X2 must be left unconnected if not used.
60 X1 input On-chip 1.8-V crystal-oscillator input; a quartz crystal or ceramic resonator must be connected across X1/X2 (with XCLKIN path disabled), or X1 must be tied to GND if not used.
61 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
62 VSS power_in Digital ground pin.
63 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground.
64 GPIO19 bidirectional General-purpose I/O 19, alternately XCLKIN (external oscillator input, path not mux-gated), SPISTEA (SPI-A slave transmit enable I/O), SCIRXDB (SCI-B receive data), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset.
65 GPIO53 bidirectional General-purpose I/O 53, alternately EQEP1I (Enhanced QEP1 index I/O) or MFSXA (McBSP transmit frame synch I/O); GPIO is default at reset.
66 GPIO39 bidirectional General-purpose I/O 39 with no other listed alternate peripheral function; GPIO is default at reset.
67 GPIO38 bidirectional General-purpose I/O 38, alternately XCLKIN (external oscillator input) or TCK (JTAG test clock with internal pullup); GPIO is default at reset.
68 GPIO34 bidirectional General-purpose I/O 34, alternately COMP2OUT (direct output of Comparator 2) or COMP3OUT (direct output of Comparator 3); GPIO is default at reset.
69 GPIO54 bidirectional General-purpose I/O 54, alternately SPISIMOA (SPI-A slave-in/master-out), EQEP2A (Enhanced QEP2 input A), or HRCAP1 (High-Resolution Input Capture 1); GPIO is default at reset.
70 GPIO37 bidirectional General-purpose I/O 37, alternately TDO (JTAG test data output, 8-mA drive, shifted out on the falling edge of TCK); GPIO is default at reset.
71 GPIO35 bidirectional General-purpose I/O 35, alternately TDI (JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK); GPIO is default at reset.
72 GPIO36 bidirectional General-purpose I/O 36, alternately TMS (JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK); GPIO is default at reset.
73 GPIO11 bidirectional General-purpose I/O 11, alternately EPWM6B (Enhanced PWM6 output B), SCIRXDB (SCI-B receive data), or ECAP1 (Enhanced Capture 1 I/O); GPIO is default at reset.
74 GPIO10 bidirectional General-purpose I/O 10, alternately EPWM6A (Enhanced PWM6 output A/HRPWM channel) or ADCSOCBO (ADC start-of-conversion B output); GPIO is default at reset.
75 GPIO55 bidirectional General-purpose I/O 55, alternately SPISOMIA (SPI-A slave out/master in), EQEP2B (Enhanced QEP2 input B), or HRCAP2 (High-Resolution Input Capture 2); GPIO is default at reset.
76 GPIO41 bidirectional General-purpose I/O 41, alternately EPWM7B (Enhanced PWM7 output B) or SCIRXDB (SCI-B receive data); GPIO is default at reset.
77 GPIO27 bidirectional General-purpose I/O 27, alternately HRCAP2 (High-Resolution Input Capture 2), EQEP2S (Enhanced QEP2 strobe), SPISTEB (SPI-B slave transmit enable I/O), or USB0DM (USB negative differential signal, enabled via the USBIOEN bit in GPACTRL2); GPIO is default at reset.
78 GPIO26 bidirectional General-purpose I/O 26, alternately ECAP3 (Enhanced Capture 3 I/O), EQEP2I (Enhanced QEP2 index), SPICLKB (SPI-B clock I/O), or USB0DP (USB positive differential signal, enabled via the USBIOEN bit in GPACTRL2); GPIO is default at reset.
79 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
80 VSS power_in Digital ground pin.
81 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground.
82 GPIO40 bidirectional General-purpose I/O 40, alternately EPWM7A (Enhanced PWM7 output A/HRPWM channel) or SCITXDB (SCI-B transmit data); GPIO is default at reset.
83 GPIO3 bidirectional General-purpose I/O 3, alternately EPWM2B (Enhanced PWM2 output B), SPISOMIA (SPI-A slave out/master in), or COMP2OUT (direct output of Comparator 2); GPIO is default at reset.
84 GPIO2 bidirectional General-purpose I/O 2, alternately EPWM2A (Enhanced PWM2 output A/HRPWM channel); GPIO is default at reset.
85 GPIO56 bidirectional General-purpose I/O 56, alternately SPICLKA (SPI-A clock I/O), EQEP2I (Enhanced QEP2 index I/O), or HRCAP3 (High-Resolution Input Capture 3); GPIO is default at reset.
86 GPIO1 bidirectional General-purpose I/O 1, alternately EPWM1B (Enhanced PWM1 output B) or COMP1OUT (direct output of Comparator 1); GPIO is default at reset.
87 GPIO0 bidirectional General-purpose I/O 0, alternately EPWM1A (Enhanced PWM1 output A/HRPWM channel); GPIO is default at reset.
88 GPIO15 bidirectional General-purpose I/O 15, alternately ECAP2 (Enhanced Capture 2 I/O), SCIRXDB (SCI-B receive data), or SPISTEB (SPI-B slave transmit enable I/O); GPIO is default at reset.
89 GPIO57 bidirectional General-purpose I/O 57, alternately SPISTEA (SPI-A slave transmit enable I/O), EQEP2S (Enhanced QEP2 strobe I/O), or HRCAP4 (High-Resolution Input Capture 4); GPIO is default at reset.
90 VREGENZ input Internal voltage regulator (VREG) enable with internal pulldown; tie directly to VSS to enable the internal 1.8-V VREG, or tie directly to VDDIO to disable the VREG and use an external 1.8-V supply.
91 VDD power_in CPU and logic digital power pin; when using the internal VREG, place a 1.2-uF capacitor between each VDD pin and ground.
92 VSS power_in Digital ground pin.
93 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
94 GPIO58 bidirectional General-purpose I/O 58, alternately MCLKRA (McBSP receive clock I/O), SCITXDB (SCI-B transmit data), or EPWM7A (Enhanced PWM7 output A/HRPWM channel); GPIO is default at reset.
95 GPIO13 bidirectional General-purpose I/O 13, alternately TZ2 (Trip Zone input 2) or SPISOMIB (SPI-B slave out/master in); GPIO is default at reset.
96 GPIO14 bidirectional General-purpose I/O 14, alternately TZ3 (Trip Zone input 3), SCITXDB (SCI-B transmit data), or SPICLKB (SPI-B clock I/O); GPIO is default at reset.
97 GPIO24 bidirectional General-purpose I/O 24, alternately ECAP1 (Enhanced Capture 1 I/O), EQEP2A (Enhanced QEP2 input A, available only on PZ/PZP packages), or SPISIMOB (SPI-B slave-in/master-out); GPIO is default at reset.
98 GPIO22 bidirectional General-purpose I/O 22, alternately EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), or SCITXDB (SCI-B transmit data); GPIO is default at reset.
99 GPIO32 bidirectional General-purpose I/O 32, alternately SDAA (I2C data open-drain bidirectional), EPWMSYNCI (Enhanced PWM external sync pulse input), or ADCSOCAO (ADC start-of-conversion A output); GPIO is default at reset.
100 GPIO33 bidirectional General-purpose I/O 33, alternately SCLA (I2C clock open-drain bidirectional), EPWMSYNCO (Enhanced PWM external sync pulse output), or ADCSOCBO (ADC start-of-conversion B output); GPIO is default at reset.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28069PZT
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28069pzt-etched.step / tms320f28069pzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28069pzt.step / tms320f28069pzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF