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TMS320F28069PZA

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28069PZA

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-100(14x14)

TMS320F28069PZA from Texas Instruments, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO42 bidirectional General-purpose I/O 42 with alternate functions EPWM8A output, TZ1 trip-zone input and COMP1OUT direct comparator 1 output; inputs are not 5-V tolerant.
2 GPIO23 bidirectional General-purpose I/O 23 with alternate functions EQEP1I index, MFSXA McBSP transmit frame sync and SCIRXDB receive data; inputs are not 5-V tolerant.
3 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
4 VSS power_in Digital ground pin.
5 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
6 GPIO20 bidirectional General-purpose I/O 20 with alternate functions EQEP1A input, MDXA McBSP transmit data and COMP1OUT comparator 1 output; inputs are not 5-V tolerant.
7 GPIO21 bidirectional General-purpose I/O 21 with alternate functions EQEP1B input, MDRA McBSP receive data and COMP2OUT comparator 2 output; inputs are not 5-V tolerant.
8 GPIO43 bidirectional General-purpose I/O 43 with alternate functions EPWM8B output, TZ2 trip-zone input and COMP2OUT comparator 2 output; inputs are not 5-V tolerant.
9 GPIO4 bidirectional General-purpose I/O 4 with alternate function EPWM3A output and HRPWM channel; inputs are not 5-V tolerant.
10 GPIO5 bidirectional General-purpose I/O 5 with alternate functions EPWM3B output, SPISIMOA and ECAP1; inputs are not 5-V tolerant.
11 XRS bidirectional Open-drain device reset input and watchdog reset output with internal pullup; a 2.2 kΩ to 10 kΩ resistor should be placed between XRS and VDDIO, and any capacitor to VSS should be 100 nF or smaller.
12 TRST input JTAG test reset with internal pulldown that must be held low during normal operation; an external pulldown resistor is required (2.2 kΩ generally offers adequate protection).
13 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
14 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
15 VSS power_in Digital ground pin.
16 ADCINA7 input ADC Group A, channel 7 analog input.
17 ADCINA6/COMP3A/AIO6 input ADC Group A, channel 6 analog input, also comparator 3A input and digital AIO6 (AIO pins have no internal pullup).
18 ADCINA5 input ADC Group A, channel 5 analog input.
19 ADCINA4/COMP2A/AIO4 input ADC Group A, channel 4 analog input, also comparator 2A input and digital AIO4 (AIO pins have no internal pullup).
20 ADCINA3 input ADC Group A, channel 3 analog input.
21 ADCINA2/COMP1A/AIO2 input ADC Group A, channel 2 analog input, also comparator 1A input and digital AIO2 (AIO pins have no internal pullup).
22 ADCINA1 input ADC Group A, channel 1 analog input.
23 ADCINA0 input ADC Group A, channel 0 analog input; ADC input range is 0 V to 3.3 V fixed or VREFHI/VREFLO ratiometric.
24 VREFHI input ADC external reference high, used only in ADC external reference mode; VREFHI must not exceed VDDA.
25 VDDA power_in Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin.
26 VSSA power_in Analog ground pin.
27 VREFLO power_in ADC external reference low.
28 ADCINB0 input ADC Group B, channel 0 analog input.
29 ADCINB1 input ADC Group B, channel 1 analog input.
30 ADCINB2/COMP1B/AIO10 input ADC Group B, channel 2 analog input, also comparator 1B input and digital AIO10 (AIO pins have no internal pullup).
31 ADCINB3 input ADC Group B, channel 3 analog input.
32 ADCINB4/COMP2B/AIO12 input ADC Group B, channel 4 analog input, also comparator 2B input and digital AIO12 (AIO pins have no internal pullup).
33 ADCINB5 input ADC Group B, channel 5 analog input.
34 ADCINB6/COMP3B/AIO14 input ADC Group B, channel 6 analog input, also comparator 3B input and digital AIO14 (AIO pins have no internal pullup).
35 ADCINB7 input ADC Group B, channel 7 analog input.
36 VSS power_in Digital ground pin.
37 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
38 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
39 GPIO25 bidirectional General-purpose I/O 25 with alternate functions ECAP2, EQEP2B input and SPISOMIB; inputs are not 5-V tolerant.
40 GPIO31 bidirectional General-purpose I/O 31 with alternate functions CANTXA CAN transmit, EQEP2S strobe and EPWM8A output; inputs are not 5-V tolerant.
41 GPIO30 bidirectional General-purpose I/O 30 with alternate functions CANRXA CAN receive, EQEP2I index and EPWM7A output; inputs are not 5-V tolerant.
42 GPIO50 bidirectional General-purpose I/O 50 with alternate functions EQEP1A input, MDXA McBSP transmit data and TZ1 trip-zone input; inputs are not 5-V tolerant.
43 GPIO29 bidirectional General-purpose I/O 29 with alternate functions SCITXDA, SCLA I2C clock (open-drain) and TZ3 trip-zone input; inputs are not 5-V tolerant.
44 GPIO12 bidirectional General-purpose I/O 12 with alternate functions TZ1 trip-zone input, SCITXDA and SPISIMOB; inputs are not 5-V tolerant.
45 TEST2 unconnected Test pin reserved for TI that must be left unconnected (datasheet lists it as I/O).
46 VDD3VFL power_in 3.3-V flash core power pin that should be connected to 3.3 V at all times.
47 VSS power_in Digital ground pin.
48 GPIO51 bidirectional General-purpose I/O 51 with alternate functions EQEP1B input, MDRA McBSP receive data and TZ2 trip-zone input; inputs are not 5-V tolerant.
49 GPIO9 bidirectional General-purpose I/O 9 with alternate functions EPWM5B output, SCITXDB and ECAP3; inputs are not 5-V tolerant.
50 GPIO28 bidirectional General-purpose I/O 28 with alternate functions SCIRXDA, SDAA I2C data (open-drain) and TZ2 trip-zone input; inputs are not 5-V tolerant.
51 GPIO18 bidirectional General-purpose I/O 18 with alternate functions SPICLKA, SCITXDB and XCLKOUT, where XCLKOUT is SYSCLKOUT divided by 1, 2 or 4 (reset value SYSCLKOUT/4).
52 GPIO17 bidirectional General-purpose I/O 17 with alternate functions SPISOMIA, and TZ3 trip-zone input; inputs are not 5-V tolerant.
53 GPIO52 bidirectional General-purpose I/O 52 with alternate functions EQEP1S strobe, MCLKXA McBSP transmit clock and TZ3 trip-zone input; inputs are not 5-V tolerant.
54 GPIO8 bidirectional General-purpose I/O 8 with alternate functions EPWM5A output and HRPWM channel and ADCSOCAO ADC start-of-conversion A; inputs are not 5-V tolerant.
55 GPIO16 bidirectional General-purpose I/O 16 with alternate functions SPISIMOA and TZ2 trip-zone input; inputs are not 5-V tolerant.
56 GPIO44 bidirectional General-purpose I/O 44 with alternate functions MFSRA McBSP receive frame sync, SCIRXDB and EPWM7B output; inputs are not 5-V tolerant.
57 GPIO7 bidirectional General-purpose I/O 7 with alternate functions EPWM4B output, SCIRXDA and ECAP2; inputs are not 5-V tolerant.
58 GPIO6 bidirectional General-purpose I/O 6 with alternate functions EPWM4A output and HRPWM channel, EPWMSYNCI and EPWMSYNCO; inputs are not 5-V tolerant.
59 X2 output On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used.
60 X1 input On-chip 1.8-V crystal oscillator input; a crystal or resonator is connected across X1 and X2, and the pin must be tied to GND if not used.
61 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
62 VSS power_in Digital ground pin.
63 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
64 GPIO19 bidirectional General-purpose I/O 19 with alternate functions XCLKIN external oscillator input, SPISTEA, SCIRXDB and ECAP1; may glitch during power-up when the VREG is used.
65 GPIO53 bidirectional General-purpose I/O 53 with alternate functions EQEP1I index and MFSXA McBSP transmit frame sync; inputs are not 5-V tolerant.
66 GPIO39 bidirectional General-purpose I/O 39 with no alternate function listed; inputs are not 5-V tolerant.
67 GPIO38 bidirectional General-purpose I/O 38 that is the default XCLKIN external clock input or TCK JTAG test clock with internal pullup; may glitch during power-up when the VREG is used.
68 GPIO34 bidirectional General-purpose I/O 34 with alternate functions COMP2OUT and COMP3OUT comparator direct outputs; may glitch during power-up when the VREG is used.
69 GPIO54 bidirectional General-purpose I/O 54 with alternate functions SPISIMOA, EQEP2A input and HRCAP1 high-resolution capture 1; inputs are not 5-V tolerant.
70 GPIO37 bidirectional General-purpose I/O 37 that is the TDO JTAG scan output with 8-mA drive; may glitch during power-up when the VREG is used.
71 GPIO35 bidirectional General-purpose I/O 35 that is the TDI JTAG test data input with internal pullup; may glitch during power-up when the VREG is used.
72 GPIO36 bidirectional General-purpose I/O 36 that is the TMS JTAG test-mode select input with internal pullup; may glitch during power-up when the VREG is used.
73 GPIO11 bidirectional General-purpose I/O 11 with alternate functions EPWM6B output, SCIRXDB and ECAP1; inputs are not 5-V tolerant.
74 GPIO10 bidirectional General-purpose I/O 10 with alternate functions EPWM6A output and HRPWM channel and ADCSOCBO ADC start-of-conversion B; inputs are not 5-V tolerant.
75 GPIO55 bidirectional General-purpose I/O 55 with alternate functions SPISOMIA, EQEP2B input and HRCAP2 high-resolution capture 2; inputs are not 5-V tolerant.
76 GPIO41 bidirectional General-purpose I/O 41 with alternate functions EPWM7B output and SCIRXDB; inputs are not 5-V tolerant.
77 GPIO27 bidirectional General-purpose I/O 27 with alternate functions HRCAP2, EQEP2S strobe, SPISTEB and USB0DM USB negative differential signal; may glitch during power-up when the VREG is used.
78 GPIO26 bidirectional General-purpose I/O 26 with alternate functions ECAP3, EQEP2I index, SPICLKB and USB0DP USB positive differential signal; may glitch during power-up when the VREG is used.
79 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
80 VSS power_in Digital ground pin.
81 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
82 GPIO40 bidirectional General-purpose I/O 40 with alternate functions EPWM7A output and SCITXDB; inputs are not 5-V tolerant.
83 GPIO3 bidirectional General-purpose I/O 3 with alternate functions EPWM2B output, SPISOMIA and COMP2OUT comparator 2 output; inputs are not 5-V tolerant.
84 GPIO2 bidirectional General-purpose I/O 2 with alternate function EPWM2A output and HRPWM channel; inputs are not 5-V tolerant.
85 GPIO56 bidirectional General-purpose I/O 56 with alternate functions SPICLKA, EQEP2I index and HRCAP3 high-resolution capture 3; inputs are not 5-V tolerant.
86 GPIO1 bidirectional General-purpose I/O 1 with alternate functions EPWM1B output and COMP1OUT comparator 1 output; inputs are not 5-V tolerant.
87 GPIO0 bidirectional General-purpose I/O 0 with alternate function EPWM1A output and HRPWM channel; inputs are not 5-V tolerant.
88 GPIO15 bidirectional General-purpose I/O 15 with alternate functions ECAP2, SCIRXDB and SPISTEB; inputs are not 5-V tolerant.
89 GPIO57 bidirectional General-purpose I/O 57 with alternate functions SPISTEA, EQEP2S strobe and HRCAP4 high-resolution capture 4; inputs are not 5-V tolerant.
90 VREGENZ input Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or tie to VDDIO to disable it and use an external 1.8-V supply.
91 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
92 VSS power_in Digital ground pin.
93 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
94 GPIO58 bidirectional General-purpose I/O 58 with alternate functions MCLKRA McBSP receive clock, SCITXDB and EPWM7A output; inputs are not 5-V tolerant.
95 GPIO13 bidirectional General-purpose I/O 13 with alternate functions TZ2 trip-zone input and SPISOMIB; inputs are not 5-V tolerant.
96 GPIO14 bidirectional General-purpose I/O 14 with alternate functions TZ3 trip-zone input, SCITXDB and SPICLKB; inputs are not 5-V tolerant.
97 GPIO24 bidirectional General-purpose I/O 24 with alternate functions ECAP1, EQEP2A input and SPISIMOB; inputs are not 5-V tolerant.
98 GPIO22 bidirectional General-purpose I/O 22 with alternate functions EQEP1S strobe, MCLKXA McBSP transmit clock and SCITXDB; inputs are not 5-V tolerant.
99 GPIO32 bidirectional General-purpose I/O 32 with alternate functions SDAA I2C data (open-drain), EPWMSYNCI and ADCSOCAO ADC start-of-conversion A; inputs are not 5-V tolerant.
100 GPIO33 bidirectional General-purpose I/O 33 with alternate functions SCLA I2C clock (open-drain), EPWMSYNCO and ADCSOCBO ADC start-of-conversion B; inputs are not 5-V tolerant.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28069PZA
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28069pza-etched.step / tms320f28069pza-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28069pza.step / tms320f28069pza.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF