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TMS320F28069PNT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28069PNT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28069PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO23/EQEP1I/MFSXA/SCIRXDB bidirectional General-purpose input/output 23 with alternate peripheral functions for enhanced quadrature encoder pulse index, McBSP frame sync, or SCI receive data.
2 VDD power_in CPU and logic digital power pin.
3 VSS power_in Digital ground pin.
4 VDDIO power_in Digital I/O buffers power pin for single supply source when VREG is enabled.
5 GPIO20/EQEP1A/MDXA/COMP1OUT bidirectional General-purpose input/output 20 with alternate functions for enhanced QEP1 input A, McBSP transmit data, or Comparator 1 output.
6 GPIO21/EQEP1B/MDRA/COMP2OUT bidirectional General-purpose input/output 21 with alternate functions for enhanced QEP1 input B, McBSP receive data, or Comparator 2 output.
7 GPIO4/EPWM3A bidirectional General-purpose input/output 4 with alternate function as enhanced PWM3 output A and HRPWM channel.
8 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose input/output 5 with alternate functions for enhanced PWM3 output B, SPI-A master-out slave-in, or enhanced capture input/output 1.
9 XRS bidirectional Device reset input/output open-drain; driven low by device during power-on or brownout reset and watchdog reset, or driven externally by external circuit.
10 TRST input JTAG test reset with internal pulldown; active-high test pin that must be maintained low during normal device operation.
11 VDDIO power_in Digital I/O buffers power pin for single supply source when VREG is enabled.
12 VDD power_in CPU and logic digital power pin.
13 VSS power_in Digital ground pin.
14 ADCINA6/COMP3A/AIO6 input ADC group A channel 6 input with alternate functions as Comparator 3A input or analog I/O 6.
15 ADCINA5 input ADC group A channel 5 input.
16 ADCINA4/COMP2A/AIO4 input ADC group A channel 4 input with alternate functions as Comparator 2A input or analog I/O 4.
17 ADCINA2/COMP1A/AIO2 input ADC group A channel 2 input with alternate functions as Comparator 1A input or analog I/O 2.
18 ADCINA1 input ADC group A channel 1 input.
19 ADCINA0/VREFHI input ADC group A channel 0 input; shares same pin with VREFHI for external ADC reference high, mutually exclusive use.
20 VDDA power_in Analog power pin; tie with 2.2-μF capacitor typical close to the pin.
21 VREFLO/VSSA power_in ADC external reference low and analog ground pin; always connected on 80-pin devices.
22 ADCINB0 input ADC group B channel 0 input.
23 ADCINB1 input ADC group B channel 1 input.
24 ADCINB2/COMP1B/AIO10 input ADC group B channel 2 input with alternate functions as Comparator 1B input or analog I/O 10.
25 ADCINB4/COMP2B/AIO12 input ADC group B channel 4 input with alternate functions as Comparator 2B input or analog I/O 12.
26 ADCINB5 input ADC group B channel 5 input.
27 ADCINB6/COMP3B/AIO14 input ADC group B channel 6 input with alternate functions as Comparator 3B input or analog I/O 14.
28 VSS power_in Digital ground pin.
29 VDD power_in CPU and logic digital power pin.
30 VDDIO power_in Digital I/O buffers power pin for single supply source when VREG is enabled.
31 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional General-purpose input/output 25 with alternate functions for enhanced capture input/output 2, enhanced QEP2 input B, or SPI-B master-in slave-out.
32 GPIO31/CANTXA/EQEP2S/EPWM8A bidirectional General-purpose input/output 31 with alternate functions for CAN transmit, enhanced QEP2 strobe, or enhanced PWM8 output A.
33 GPIO30/CANRXA/EQEP2I/EPWM7A bidirectional General-purpose input/output 30 with alternate functions for CAN receive, enhanced QEP2 index, or enhanced PWM7 output A.
34 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose input/output 29 with alternate functions for SCI-A transmit, I2C clock open-drain bidirectional, or Trip Zone input 3.
35 GPIO12/TZ1/SCITXDA/SPISIMOB bidirectional General-purpose input/output 12 with alternate functions for Trip Zone input 1, SCI-A transmit, or SPI-B master-in slave-out.
36 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
37 VDD3VFL power_in 3.3-V flash core power pin; must be connected to 3.3 V at all times.
38 VSS power_in Digital ground pin.
39 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional General-purpose input/output 9 with alternate functions for enhanced PWM5 output B, SCI-B transmit, or enhanced capture input/output 3.
40 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose input/output 28 with alternate functions for SCI-A receive, I2C data open-drain bidirectional, or Trip Zone input 2.
41 GPIO18/SPICLKA/SCITXDB/XCLKOUT bidirectional General-purpose input/output 18 with alternate functions for SPI-A clock, SCI-B transmit, or output clock derived from SYSCLKOUT.
42 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose input/output 17 with alternate functions for SPI-A master-in slave-out or Trip Zone input 3.
43 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose input/output 8 with alternate functions for enhanced PWM5 output A and HRPWM channel or ADC start-of-conversion A.
44 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose input/output 16 with alternate functions for SPI-A master-out slave-in or Trip Zone input 2.
45 GPIO7/EPWM4B/SCIRXDA/ECAP2 bidirectional General-purpose input/output 7 with alternate functions for enhanced PWM4 output B, SCI-A receive, or enhanced capture input/output 2.
46 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose input/output 6 with alternate functions for enhanced PWM4 output A and HRPWM channel, enhanced PWM sync pulse input, or output.
47 X2 output On-chip crystal-oscillator output; quartz crystal or ceramic resonator connected across X1 and X2, left unconnected if not used.
48 X1 input On-chip 1.8-V crystal-oscillator input; quartz crystal or ceramic resonator connected across X1 and X2, tied to GND if not used.
49 VDDIO power_in Digital I/O buffers power pin for single supply source when VREG is enabled.
50 VSS power_in Digital ground pin.
51 VDD power_in CPU and logic digital power pin.
52 GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1 bidirectional General-purpose input/output 19 with alternate functions for external oscillator input, SPI-A transmit enable, SCI-B receive, or enhanced capture input/output 1.
53 GPIO39 bidirectional General-purpose input/output 39.
54 GPIO38/XCLKIN/TCK bidirectional General-purpose input/output 38 with alternate functions for external oscillator input or JTAG test clock with internal pullup.
55 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose input/output 34 with alternate output functions for Comparator 2 or Comparator 3 direct outputs.
56 GPIO37/TDO tri_state General-purpose input/output 37 with alternate function as JTAG scan out, test data output; contents of selected register shifted on TCK falling edge with 8-mA drive.
57 GPIO35/TDI input General-purpose input/output 35 with alternate function as JTAG test data input; clocked into selected register on TCK rising edge with internal pullup.
58 GPIO36/TMS input General-purpose input/output 36 with alternate function as JTAG test-mode select; clocked into TAP controller on TCK rising edge with internal pullup.
59 GPIO11/EPWM6B/SCIRXDB/ECAP1 bidirectional General-purpose input/output 11 with alternate functions for enhanced PWM6 output B, SCI-B receive, or enhanced capture input/output 1.
60 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose input/output 10 with alternate functions for enhanced PWM6 output A and HRPWM channel or ADC start-of-conversion B.
61 GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM bidirectional General-purpose input/output 27 with alternate functions for high-resolution input capture 2, enhanced QEP2 strobe, SPI-B transmit enable, or USB negative differential signal.
62 GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP bidirectional General-purpose input/output 26 with alternate functions for enhanced capture input/output 3, enhanced QEP2 index, SPI-B clock, or USB positive differential signal.
63 VDDIO power_in Digital I/O buffers power pin for single supply source when VREG is enabled.
64 VSS power_in Digital ground pin.
65 VDD power_in CPU and logic digital power pin.
66 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose input/output 3 with alternate functions for enhanced PWM2 output B, SPI-A master-in slave-out, or Comparator 2 direct output.
67 GPIO2/EPWM2A bidirectional General-purpose input/output 2 with alternate function as enhanced PWM2 output A and HRPWM channel.
68 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose input/output 1 with alternate functions for enhanced PWM1 output B or Comparator 1 direct output.
69 GPIO0/EPWM1A bidirectional General-purpose input/output 0 with alternate function as enhanced PWM1 output A and HRPWM channel.
70 GPIO15/ECAP2/SCIRXDB/SPISTEB bidirectional General-purpose input/output 15 with alternate functions for enhanced capture input/output 2, SCI-B receive, or SPI-B transmit enable.
71 VREGENZ input Internal voltage regulator enable with internal pulldown; tie to VSS to enable 1.8-V VREG or tie to VDDIO to disable VREG and use external 1.8-V supply.
72 VDD power_in CPU and logic digital power pin.
73 VSS power_in Digital ground pin.
74 VDDIO power_in Digital I/O buffers power pin for single supply source when VREG is enabled.
75 GPIO13/TZ2/SPISOMIB bidirectional General-purpose input/output 13 with alternate functions for Trip Zone input 2 or SPI-B master-in slave-out.
76 GPIO14/TZ3/SCITXDB/SPICLKB bidirectional General-purpose input/output 14 with alternate functions for Trip Zone input 3, SCI-B transmit, or SPI-B clock.
77 GPIO24/ECAP1/EQEP2A/SPISIMOB bidirectional General-purpose input/output 24 with alternate functions for enhanced capture input/output 1, enhanced QEP2 input A, or SPI-B master-out slave-in.
78 GPIO22/EQEP1S/MCLKXA/SCITXDB bidirectional General-purpose input/output 22 with alternate functions for enhanced QEP1 strobe, McBSP transmit clock, or SCI-B transmit data.
79 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose input/output 32 with alternate functions for I2C data open-drain bidirectional, enhanced PWM external sync pulse input, or ADC start-of-conversion A.
80 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose input/output 33 with alternate functions for I2C clock open-drain bidirectional, enhanced PWM external sync pulse output, or ADC start-of-conversion B.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28069PNT
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28069pnt-etched.step / tms320f28069pnt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28069pnt.step / tms320f28069pnt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF