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TMS320F28069FPZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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TMS320F28069FPZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F28069FPZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO42 bidirectional General-purpose input/output 42 with configurable functions including EPWM8A output, TZ1 trip zone input, and COMP1OUT comparator output.
2 GPIO23 bidirectional General-purpose input/output 23 with configurable functions including EQEP1I index input, MFSXA McBSP frame synch, and SCIRXDB SCI-B receive data.
3 VDD power_in CPU and Logic Digital Power Pin; place one 1.2-µF capacitor between each VDD pin and ground when using internal VREG.
4 VSS power_in Digital Ground Pin.
5 VDDIO power_in Digital I/O Buffers Power Pin; place a decoupling capacitor on each pin for proper system voltage regulation.
6 GPIO20 bidirectional General-purpose input/output 20 with configurable functions including EQEP1A encoder input, MDXA McBSP data output, and COMP1OUT comparator output.
7 GPIO21 bidirectional General-purpose input/output 21 with configurable functions including EQEP1B encoder input, MDRA McBSP data input, and COMP2OUT comparator output.
8 GPIO43 bidirectional General-purpose input/output 43 with configurable functions including EPWM8B output, TZ2 trip zone input, and COMP2OUT comparator output.
9 GPIO4 bidirectional General-purpose input/output 4 with configurable functions including EPWM3A enhanced PWM output and HRPWM channel.
10 GPIO5 bidirectional General-purpose input/output 5 with configurable functions including EPWM3B output, SPISIMOA SPI data, and ECAP1 enhanced capture input.
11 XRS bidirectional Device Reset input/Watchdog Reset output with open-drain configuration; external 2.2-kΩ to 10-kΩ resistor required to VDDIO.
12 TRST input JTAG test reset input with internal pulldown; active-high test pin that must be maintained low during normal device operation with external pulldown resistor required.
13 VDDIO power_in Digital I/O Buffers Power Pin; place a decoupling capacitor on each pin for proper system voltage regulation.
14 VDD power_in CPU and Logic Digital Power Pin; place one 1.2-µF capacitor between each VDD pin and ground when using internal VREG.
15 VSS power_in Digital Ground Pin.
16 ADCINA7 input ADC Group A Channel 7 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
17 ADCINA6 input ADC Group A Channel 6 analog input with alternate functions for COMP3A comparator input and AIO6 digital I/O.
18 ADCINA5 input ADC Group A Channel 5 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
19 ADCINA4 input ADC Group A Channel 4 analog input with alternate functions for COMP2A comparator input and AIO4 digital I/O.
20 ADCINA3 input ADC Group A Channel 3 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
21 ADCINA2 input ADC Group A Channel 2 analog input with alternate functions for COMP1A comparator input and AIO2 digital I/O.
22 ADCINA1 input ADC Group A Channel 1 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
23 ADCINA0 input ADC Group A Channel 0 analog input for 12-bit analog-to-digital converter; VREFHI and ADCINA0 share same pin on 80-pin devices and use is mutually exclusive.
24 VREFHI input ADC External Reference High used only when in ADC external reference mode; VREFHI must not exceed VDDA.
25 VDDA power_in Analog Power Pin; tie with 2.2-µF capacitor (typical) close to the pin for proper analog circuit operation.
26 VSSA power_in Analog Ground Pin; always connected to VREFLO on 80-pin devices.
27 VREFLO input ADC External Reference Low used for ratiometric ADC conversions; always connected to VSSA on 80-pin devices.
28 ADCINB0 input ADC Group B Channel 0 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
29 ADCINB1 input ADC Group B Channel 1 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
30 ADCINB2 input ADC Group B Channel 2 analog input with alternate functions for COMP1B comparator input and AIO10 digital I/O.
31 ADCINB3 input ADC Group B Channel 3 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
32 ADCINB4 input ADC Group B Channel 4 analog input with alternate functions for COMP2B comparator input and AIO12 digital I/O.
33 ADCINB5 input ADC Group B Channel 5 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
34 ADCINB6 input ADC Group B Channel 6 analog input with alternate functions for COMP3B comparator input and AIO14 digital I/O.
35 ADCINB7 input ADC Group B Channel 7 analog input for 12-bit analog-to-digital converter with 0 V to 3.3 V full range.
36 VSS power_in Digital Ground Pin.
37 VDD power_in CPU and Logic Digital Power Pin; place one 1.2-µF capacitor between each VDD pin and ground when using internal VREG.
38 VDDIO power_in Digital I/O Buffers Power Pin; place a decoupling capacitor on each pin for proper system voltage regulation.
39 GPIO25 bidirectional General-purpose input/output 25 with configurable functions including ECAP2 enhanced capture, EQEP2B encoder input, and SPISOMIB SPI data.
40 GPIO31 bidirectional General-purpose input/output 31 with configurable functions including CANTXA CAN transmit, EQEP2S encoder strobe, and EPWM8A output.
41 GPIO30 bidirectional General-purpose input/output 30 with configurable functions including CANRXA CAN receive, EQEP2I encoder index, and EPWM7A output.
42 GPIO50 bidirectional General-purpose input/output 50 with configurable functions including EQEP1A encoder input, MDXA McBSP data output, and TZ1 trip zone input.
43 GPIO29 bidirectional General-purpose input/output 29 with configurable functions including SCITXDA SCI transmit, SCLA I2C open-drain clock, and TZ3 trip zone input.
44 GPIO12 bidirectional General-purpose input/output 12 with configurable functions including TZ1 trip zone input, SCITXDA SCI transmit, and SPISIMOB SPI data.
45 TEST2 unconnected Test Pin reserved for Texas Instruments; must be left unconnected.
46 VDD3VFL power_in 3.3-V Flash Core Power Pin that must be connected to 3.3 V at all times for proper flash memory operation.
47 VSS power_in Digital Ground Pin.
48 GPIO51 bidirectional General-purpose input/output 51 with configurable functions including EQEP1B encoder input, MDRA McBSP data input, and TZ2 trip zone input.
49 GPIO9 bidirectional General-purpose input/output 9 with configurable functions including EPWM5B output, SCITXDB SCI transmit, and ECAP3 enhanced capture.
50 GPIO28 bidirectional General-purpose input/output 28 with configurable functions including SCIRXDA SCI receive, SDAA I2C open-drain data, and TZ2 trip zone input.
51 GPIO18 bidirectional General-purpose input/output 18 with configurable functions including SPICLKA SPI clock, SCITXDB SCI transmit, and XCLKOUT clock output.
52 GPIO17 bidirectional General-purpose input/output 17 with configurable functions including SPISOMIA SPI data and TZ3 trip zone input.
53 GPIO52 bidirectional General-purpose input/output 52 with configurable functions including EQEP1S encoder strobe, MCLKXA McBSP clock, and TZ3 trip zone input.
54 GPIO8 bidirectional General-purpose input/output 8 with configurable functions including EPWM5A output and ADCSOCAO ADC start-of-conversion trigger.
55 GPIO16 bidirectional General-purpose input/output 16 with configurable functions including SPISIMOA SPI data and TZ2 trip zone input.
56 GPIO44 bidirectional General-purpose input/output 44 with configurable functions including MFSRA McBSP frame synch, SCIRXDB SCI receive, and EPWM7B output.
57 GPIO7 bidirectional General-purpose input/output 7 with configurable functions including EPWM4B output, SCIRXDA SCI receive, and ECAP2 enhanced capture.
58 GPIO6 bidirectional General-purpose input/output 6 with configurable functions including EPWM4A output, EPWMSYNCI external sync pulse input, and EPWMSYNCO external sync pulse output.
59 X2 output On-chip crystal-oscillator output; quartz crystal or ceramic resonator must be connected between X1 and X2; leave unconnected if not used.
60 X1 input On-chip 1.8-V crystal-oscillator input; quartz crystal or ceramic resonator must be connected across X1 and X2; must be tied to GND if not used.
61 VDDIO power_in Digital I/O Buffers Power Pin; place a decoupling capacitor on each pin for proper system voltage regulation.
62 VSS power_in Digital Ground Pin.
63 VDD power_in CPU and Logic Digital Power Pin; place one 1.2-µF capacitor between each VDD pin and ground when using internal VREG.
64 GPIO19 bidirectional General-purpose input/output 19 with configurable functions including external XCLKIN oscillator input, SPISTEA SPI transmit enable, SCIRXDB SCI receive, and ECAP1 capture.
65 GPIO53 bidirectional General-purpose input/output 53 with configurable functions including EQEP1I encoder index and MFSXA McBSP frame synch.
66 GPIO39 bidirectional General-purpose input/output 39 with no alternate peripheral functions.
67 GPIO38 bidirectional General-purpose input/output 38 with configurable functions including XCLKIN external oscillator input and TCK JTAG test clock.
68 GPIO34 bidirectional General-purpose input/output 34 with configurable functions including COMP2OUT and COMP3OUT direct comparator outputs.
69 GPIO54 bidirectional General-purpose input/output 54 with configurable functions including SPISIMOA SPI data, EQEP2A encoder input, and HRCAP1 high-resolution capture.
70 GPIO37 output General-purpose input/output 37 with primary function as TDO JTAG test data output with 8-mA drive and tri-state capability.
71 GPIO35 input General-purpose input/output 35 with primary function as TDI JTAG test data input with internal pullup.
72 GPIO36 input General-purpose input/output 36 with primary function as TMS JTAG test-mode select input with internal pullup.
73 GPIO11 bidirectional General-purpose input/output 11 with configurable functions including EPWM6B output, SCIRXDB SCI receive, and ECAP1 enhanced capture.
74 GPIO10 bidirectional General-purpose input/output 10 with configurable functions including EPWM6A output and ADCSOCBO ADC start-of-conversion trigger.
75 GPIO55 bidirectional General-purpose input/output 55 with configurable functions including SPISOMIA SPI data, EQEP2B encoder input, and HRCAP2 high-resolution capture.
76 GPIO41 bidirectional General-purpose input/output 41 with configurable functions including EPWM7B output and SCIRXDB SCI receive.
77 GPIO27 bidirectional General-purpose input/output 27 with configurable functions including HRCAP2 high-resolution capture, EQEP2S encoder strobe, SPISTEB SPI transmit enable, and USB0DM USB differential signal.
78 GPIO26 bidirectional General-purpose input/output 26 with configurable functions including ECAP3 capture, EQEP2I encoder index, SPICLKB SPI clock, and USB0DP USB differential signal.
79 VDDIO power_in Digital I/O Buffers Power Pin; place a decoupling capacitor on each pin for proper system voltage regulation.
80 VSS power_in Digital Ground Pin.
81 VDD power_in CPU and Logic Digital Power Pin; place one 1.2-µF capacitor between each VDD pin and ground when using internal VREG.
82 GPIO40 bidirectional General-purpose input/output 40 with configurable functions including EPWM7A output and SCITXDB SCI transmit.
83 GPIO3 bidirectional General-purpose input/output 3 with configurable functions including EPWM2B output, SPISOMIA SPI data, and COMP2OUT comparator output.
84 GPIO2 bidirectional General-purpose input/output 2 with configurable functions including EPWM2A output and HRPWM channel.
85 GPIO56 bidirectional General-purpose input/output 56 with configurable functions including SPICLKA SPI clock, EQEP2I encoder index, and HRCAP3 high-resolution capture.
86 GPIO1 bidirectional General-purpose input/output 1 with configurable functions including EPWM1B output and COMP1OUT comparator output.
87 GPIO0 bidirectional General-purpose input/output 0 with configurable functions including EPWM1A output and HRPWM channel.
88 GPIO15 bidirectional General-purpose input/output 15 with configurable functions including ECAP2 enhanced capture, SCIRXDB SCI receive, and SPISTEB SPI transmit enable.
89 GPIO57 bidirectional General-purpose input/output 57 with configurable functions including SPISTEA SPI transmit enable, EQEP2S encoder strobe, and HRCAP4 high-resolution capture.
90 VREGENZ input Internal voltage regulator (VREG) enable input with internal pulldown; tie to VSS to enable 1.8-V VREG or to VDDIO to disable and use external 1.8-V supply.
91 VDD power_in CPU and Logic Digital Power Pin; place one 1.2-µF capacitor between each VDD pin and ground when using internal VREG.
92 VSS power_in Digital Ground Pin.
93 VDDIO power_in Digital I/O Buffers Power Pin; place a decoupling capacitor on each pin for proper system voltage regulation.
94 GPIO58 bidirectional General-purpose input/output 58 with configurable functions including MCLKRA McBSP receive clock, SCITXDB SCI transmit, and EPWM7A output.
95 GPIO13 bidirectional General-purpose input/output 13 with configurable functions including TZ2 trip zone input and SPISOMIB SPI data.
96 GPIO14 bidirectional General-purpose input/output 14 with configurable functions including TZ3 trip zone input, SCITXDB SCI transmit, and SPICLKB SPI clock.
97 GPIO24 bidirectional General-purpose input/output 24 with configurable functions including ECAP1 enhanced capture, EQEP2A encoder input, and SPISIMOB SPI data.
98 GPIO22 bidirectional General-purpose input/output 22 with configurable functions including EQEP1S encoder strobe, MCLKXA McBSP clock, and SCITXDB SCI transmit.
99 GPIO32 bidirectional General-purpose input/output 32 with configurable functions including SDAA I2C open-drain data, EPWMSYNCI external sync input, and ADCSOCAO ADC start-of-conversion trigger.
100 GPIO33 bidirectional General-purpose input/output 33 with configurable functions including SCLA I2C open-drain clock, EPWMSYNCO external sync output, and ADCSOCBO ADC start-of-conversion trigger.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28069FPZT
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28069fpzt-etched.step / tms320f28069fpzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28069fpzt.step / tms320f28069fpzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF