component
TMS320F28069FPNT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28069FPNT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)
TMS320F28069FPNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO23/EQEP1I/MFSXA/SCIRXDB | bidirectional | General-purpose I/O 23; alternate functions: eQEP1 index I/O, McBSP transmit frame sync I/O, SCI-B receive input; internal pullup enabled at reset. |
| 2 | VDD | power_in | 1.8-V CPU and logic digital power; place one 1.2-µF decoupling capacitor between each VDD pin and ground. |
| 3 | VSS | power_in | Digital ground reference pin. |
| 4 | VDDIO | power_in | 3.3-V digital I/O buffer power; single supply source when VREG is enabled; place a decoupling capacitor on each pin. |
| 5 | GPIO20/EQEP1A/MDXA/COMP1OUT | bidirectional | General-purpose I/O 20; alternate functions: eQEP1 input A, McBSP transmit serial data output, Comparator 1 direct output; internal pullup enabled at reset. |
| 6 | GPIO21/EQEP1B/MDRA/COMP2OUT | bidirectional | General-purpose I/O 21; alternate functions: eQEP1 input B, McBSP receive serial data input, Comparator 2 direct output; internal pullup enabled at reset. |
| 7 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4; alternate function: ePWM3 output A with HRPWM channel; pullup not enabled at reset. |
| 8 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | General-purpose I/O 5; alternate functions: ePWM3 output B, SPI-A slave in/master out I/O, eCAP1 input/output; pullup not enabled at reset. |
| 9 | XRS | bidirectional | Device reset input and watchdog reset open-drain output; driven low by device during POR/BOR or watchdog reset (512 OSCCLK cycles); requires 2.2-kΩ to 10-kΩ pullup resistor to VDDIO; internal pullup. |
| 10 | TRST | input | JTAG test reset with internal pulldown; active-high: driven high grants scan system control; must be held low during normal operation with external 2.2-kΩ pulldown resistor. |
| 11 | VDDIO | power_in | 3.3-V digital I/O buffer power; single supply source when VREG is enabled; place a decoupling capacitor on each pin. |
| 12 | VDD | power_in | 1.8-V CPU and logic digital power; place one 1.2-µF decoupling capacitor between each VDD pin and ground. |
| 13 | VSS | power_in | Digital ground reference pin. |
| 14 | ADCINA6/COMP3A/AIO6 | input | ADC group A channel 6 analog input (0 V to 3.3 V fixed range); alternate: Comparator 3A input, Digital AIO6 bidirectional; no internal pullup on AIO pins. |
| 15 | ADCINA5 | input | ADC group A channel 5 analog input (0 V to 3.3 V fixed range, 12-bit, up to 3.46 MSPS). |
| 16 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input (0 V to 3.3 V fixed range); alternate: Comparator 2A input, Digital AIO4 bidirectional; no internal pullup on AIO pins. |
| 17 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input (0 V to 3.3 V fixed range); alternate: Comparator 1A input, Digital AIO2 bidirectional; no internal pullup on AIO pins. |
| 18 | ADCINA1 | input | ADC group A channel 1 analog input (0 V to 3.3 V fixed range). |
| 19 | ADCINA0/VREFHI | passive | ADC group A channel 0 input and ADC external reference high (for ratiometric mode) share this pin on the 80-pin PN package; their use is mutually exclusive. |
| 20 | VDDA | power_in | Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin. |
| 21 | VREFLO/VSSA | power_in | ADC external reference low and analog ground; VREFLO is always connected to VSSA on the 80-pin PN package. |
| 22 | ADCINB0 | input | ADC group B channel 0 analog input (0 V to 3.3 V fixed range). |
| 23 | ADCINB1 | input | ADC group B channel 1 analog input (0 V to 3.3 V fixed range). |
| 24 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input (0 V to 3.3 V); alternate: Comparator 1B input, Digital AIO10 bidirectional; no internal pullup on AIO pins. |
| 25 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input (0 V to 3.3 V); alternate: Comparator 2B input, Digital AIO12 bidirectional; no internal pullup on AIO pins. |
| 26 | ADCINB5 | input | ADC group B channel 5 analog input (0 V to 3.3 V fixed range). |
| 27 | ADCINB6/COMP3B/AIO14 | input | ADC group B channel 6 analog input (0 V to 3.3 V); alternate: Comparator 3B input, Digital AIO14 bidirectional; no internal pullup on AIO pins. |
| 28 | VSS | power_in | Digital ground reference pin. |
| 29 | VDD | power_in | 1.8-V CPU and logic digital power; place one 1.2-µF decoupling capacitor between each VDD pin and ground. |
| 30 | VDDIO | power_in | 3.3-V digital I/O buffer power; single supply source when VREG is enabled; place a decoupling capacitor on each pin. |
| 31 | GPIO25/ECAP2/EQEP2B/SPISOMIB | bidirectional | General-purpose I/O 25; alternate functions: eCAP2 I/O, eQEP2 input B (PZ/PZP packages only), SPI-B slave out/master in; internal pullup enabled at reset. |
| 32 | GPIO31/CANTXA/EQEP2S/EPWM8A | bidirectional | General-purpose I/O 31; alternate functions: CAN transmit output, eQEP2 strobe (PZ/PZP packages only), ePWM8 output A with HRPWM; internal pullup enabled at reset. |
| 33 | GPIO30/CANRXA/EQEP2I/EPWM7A | bidirectional | General-purpose I/O 30; alternate functions: CAN receive input, eQEP2 index I/O (PZ/PZP packages only), ePWM7 output A with HRPWM; internal pullup enabled at reset. |
| 34 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29; alternate functions: SCI-A transmit output, I2C clock open-drain I/O, Trip Zone input 3; internal pullup enabled at reset. |
| 35 | GPIO12/TZ1/SCITXDA/SPISIMOB | bidirectional | General-purpose I/O 12; alternate functions: Trip Zone input 1, SCI-A transmit output, SPI-B slave in/master out; internal pullup enabled at reset. |
| 36 | TEST2 | unconnected | Test pin reserved for TI; must be left unconnected. |
| 37 | VDD3VFL | power_in | 3.3-V Flash core power pin; must be connected to 3.3 V at all times. |
| 38 | VSS | power_in | Digital ground reference pin. |
| 39 | GPIO9/EPWM5B/SCITXDB/ECAP3 | bidirectional | General-purpose I/O 9; alternate functions: ePWM5 output B, SCI-B transmit output, eCAP3 I/O; pullup not enabled at reset. |
| 40 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28; alternate functions: SCI-A receive input, I2C data open-drain bidirectional, Trip Zone input 2; internal pullup enabled at reset. |
| 41 | GPIO18/SPICLKA/SCITXDB/XCLKOUT | bidirectional | General-purpose I/O 18; alternate functions: SPI-A clock I/O, SCI-B transmit output, XCLKOUT (SYSCLKOUT/1, /2, or /4; default /4 at reset; tri-state when disabled via XCLKOUTDIV=3); internal pullup enabled. |
| 42 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17; alternate functions: SPI-A slave out/master in I/O, Trip Zone input 3; internal pullup enabled at reset. |
| 43 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | General-purpose I/O 8; alternate functions: ePWM5 output A with HRPWM, ADC start-of-conversion A output; pullup not enabled at reset. |
| 44 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16; alternate functions: SPI-A slave in/master out I/O, Trip Zone input 2; internal pullup enabled at reset. |
| 45 | GPIO7/EPWM4B/SCIRXDA/ECAP2 | bidirectional | General-purpose I/O 7; alternate functions: ePWM4 output B, SCI-A receive input, eCAP2 I/O; pullup not enabled at reset. |
| 46 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6; alternate functions: ePWM4 output A with HRPWM, external ePWM sync pulse input, external ePWM sync pulse output; pullup not enabled at reset. |
| 47 | X2 | output | On-chip crystal oscillator output; connect a quartz crystal or ceramic resonator between X1 and X2; leave unconnected if crystal oscillator is not used. |
| 48 | X1 | input | On-chip 1.8-V crystal oscillator input; connect a quartz crystal or resonator between X1 and X2; tie to GND if not used. |
| 49 | VDDIO | power_in | 3.3-V digital I/O buffer power; single supply source when VREG is enabled; place a decoupling capacitor on each pin. |
| 50 | VSS | power_in | Digital ground reference pin. |
| 51 | VDD | power_in | 1.8-V CPU and logic digital power; place one 1.2-µF decoupling capacitor between each VDD pin and ground. |
| 52 | GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1 | bidirectional | General-purpose I/O 19; XCLKIN path from this pin to the clock block is not gated by the mux; alternate: SPI-A slave transmit enable I/O, SCI-B receive input, eCAP1 I/O; may glitch during power-up when on-chip VREG is used. |
| 53 | GPIO39 | bidirectional | General-purpose I/O 39; no peripheral alternate functions defined; internal pullup enabled at reset. |
| 54 | GPIO38/XCLKIN/TCK | bidirectional | General-purpose I/O 38; alternate functions: external clock input (XCLKIN, default source via XCLKINSEL bit), JTAG test clock (TCK) with internal pullup; may glitch during power-up when on-chip VREG is used. |
| 55 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | General-purpose I/O 34; alternate functions: Comparator 2 direct output, Comparator 3 direct output; may glitch during power-up when on-chip VREG is used. |
| 56 | GPIO37/TDO | bidirectional | General-purpose I/O 37; alternate function: JTAG scan-out test data output (TDO), contents shifted out on falling edge of TCK with 8-mA drive; may glitch during power-up when on-chip VREG is used. |
| 57 | GPIO35/TDI | bidirectional | General-purpose I/O 35; alternate function: JTAG test data input (TDI) with internal pullup, clocked into selected register on rising edge of TCK; may glitch during power-up when on-chip VREG is used. |
| 58 | GPIO36/TMS | bidirectional | General-purpose I/O 36; alternate function: JTAG test-mode select (TMS) with internal pullup, serial control input clocked into TAP controller on rising edge of TCK; may glitch during power-up when on-chip VREG is used. |
| 59 | GPIO11/EPWM6B/SCIRXDB/ECAP1 | bidirectional | General-purpose I/O 11; alternate functions: ePWM6 output B, SCI-B receive input, eCAP1 I/O; pullup not enabled at reset. |
| 60 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | General-purpose I/O 10; alternate functions: ePWM6 output A with HRPWM, ADC start-of-conversion B output; pullup not enabled at reset. |
| 61 | GPIO27/HRCAP2/SPISTEB/USB0DM | bidirectional | General-purpose I/O 27; alternate functions: HRCAP2 input, SPI-B slave transmit enable I/O, USB0 negative differential signal (enabled via USBIOEN bit in GPACTRL2); may glitch during power-up when on-chip VREG is used. |
| 62 | GPIO26/ECAP3/SPICLKB/USB0DP | bidirectional | General-purpose I/O 26; alternate functions: eCAP3 I/O, SPI-B clock I/O, USB0 positive differential signal (enabled via USBIOEN bit in GPACTRL2); may glitch during power-up when on-chip VREG is used. |
| 63 | VDDIO | power_in | 3.3-V digital I/O buffer power; single supply source when VREG is enabled; place a decoupling capacitor on each pin. |
| 64 | VSS | power_in | Digital ground reference pin. |
| 65 | VDD | power_in | 1.8-V CPU and logic digital power; place one 1.2-µF decoupling capacitor between each VDD pin and ground. |
| 66 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | General-purpose I/O 3; alternate functions: ePWM2 output B, SPI-A slave out/master in I/O, Comparator 2 direct output; pullup not enabled at reset. |
| 67 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2; alternate function: ePWM2 output A with HRPWM channel; pullup not enabled at reset. |
| 68 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1; alternate functions: ePWM1 output B, Comparator 1 direct output; pullup not enabled at reset. |
| 69 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0; alternate function: ePWM1 output A with HRPWM channel; pullup not enabled at reset. |
| 70 | GPIO15/ECAP2/SCIRXDB/SPISTEB | bidirectional | General-purpose I/O 15; alternate functions: eCAP2 I/O, SCI-B receive input, SPI-B slave transmit enable I/O; internal pullup enabled at reset. |
| 71 | VREGENZ | input | Internal voltage regulator enable with internal pulldown; tie low (to VSS) to enable internal 1.8-V VREG; tie high (to VDDIO) to disable VREG and use an external 1.8-V supply. |
| 72 | VDD | power_in | 1.8-V CPU and logic digital power; place one 1.2-µF decoupling capacitor between each VDD pin and ground. |
| 73 | VSS | power_in | Digital ground reference pin. |
| 74 | VDDIO | power_in | 3.3-V digital I/O buffer power; single supply source when VREG is enabled; place a decoupling capacitor on each pin. |
| 75 | GPIO13/TZ2/SPISOMIB | bidirectional | General-purpose I/O 13; alternate functions: Trip Zone input 2, SPI-B slave out/master in I/O; internal pullup enabled at reset. |
| 76 | GPIO14/TZ3/SCITXDB/SPICLKB | bidirectional | General-purpose I/O 14; alternate functions: Trip Zone input 3, SCI-B transmit output, SPI-B clock I/O; internal pullup enabled at reset. |
| 77 | GPIO24/ECAP1/EQEP2A/SPISIMOB | bidirectional | General-purpose I/O 24; alternate functions: eCAP1 I/O, eQEP2 input A (PZ/PZP packages only), SPI-B slave in/master out I/O; internal pullup enabled at reset. |
| 78 | GPIO22/EQEP1S/MCLKXA/SCITXDB | bidirectional | General-purpose I/O 22; alternate functions: eQEP1 strobe I/O, McBSP transmit clock I/O, SCI-B transmit output; internal pullup enabled at reset. |
| 79 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32; alternate functions: I2C data open-drain bidirectional, ePWM external sync pulse input, ADC start-of-conversion A output; internal pullup enabled at reset. |
| 80 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33; alternate functions: I2C clock open-drain bidirectional, ePWM external sync pulse output, ADC start-of-conversion B output; internal pullup enabled at reset. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
TMS320F28069FPNT - Footprint:
Package_QFP:LQFP-80_12x12mm_P0.5mm - 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
tms320f28069fpnt-etched.step/tms320f28069fpnt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28069fpnt.step/tms320f28069fpnt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (206 pp, sha256
3033efed856fc72a, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).