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TMS320F28062UPZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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TMS320F28062UPZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-100(14x14)

TMS320F28062UPZT from Texas Instruments, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO42 bidirectional General-purpose I/O 42 with mux options EPWM8A, TZ1 and COMP1OUT.
2 GPIO23 bidirectional General-purpose I/O 23 with mux options EQEP1I, MFSXA and SCIRXDB.
3 VDD power_in CPU and logic digital power pin; with internal VREG place one 1.2-µF capacitor between each VDD pin and ground.
4 VSS power_in Digital ground pin.
5 VDDIO power_in Digital I/O buffers power pin, single supply source when VREG is enabled; place a decoupling capacitor on each pin.
6 GPIO20 bidirectional General-purpose I/O 20 with mux options EQEP1A, MDXA and COMP1OUT.
7 GPIO21 bidirectional General-purpose I/O 21 with mux options EQEP1B, MDRA and COMP2OUT.
8 GPIO43 bidirectional General-purpose I/O 43 with mux options EPWM8B, TZ2 and COMP2OUT.
9 GPIO4 bidirectional General-purpose I/O 4 with mux option EPWM3A (HRPWM channel).
10 GPIO5 bidirectional General-purpose I/O 5 with mux options EPWM3B, SPISIMOA and ECAP1.
11 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal pullup); use a 2.2 kΩ to 10 kΩ resistor to VDDIO and any filter capacitor of 100 nF or smaller to VSS.
12 TRST input JTAG test reset with internal pulldown; active-high, must be kept low during normal operation, external pulldown required (2.2 kΩ generally adequate).
13 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
14 VDD power_in CPU and logic digital power pin; 1.2-µF capacitor to ground when using internal VREG.
15 VSS power_in Digital ground pin.
16 ADCINA7 input ADC Group A, channel 7 input.
17 ADCINA6 input ADC Group A channel 6 input, shared with COMP3A comparator input and AIO6 digital I/O.
18 ADCINA5 input ADC Group A, channel 5 input.
19 ADCINA4 input ADC Group A channel 4 input, shared with COMP2A comparator input and AIO4 digital I/O.
20 ADCINA3 input ADC Group A, channel 3 input.
21 ADCINA2 input ADC Group A channel 2 input, shared with COMP1A comparator input and AIO2 digital I/O.
22 ADCINA1 input ADC Group A, channel 1 input.
23 ADCINA0 input ADC Group A, channel 0 input.
24 VREFHI input ADC external reference high, only used in ADC external reference mode and must not exceed VDDA.
25 VDDA power_in Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin.
26 VSSA power_in Analog ground pin.
27 VREFLO input ADC external reference low.
28 ADCINB0 input ADC Group B, channel 0 input.
29 ADCINB1 input ADC Group B, channel 1 input.
30 ADCINB2 input ADC Group B channel 2 input, shared with COMP1B comparator input and AIO10 digital I/O.
31 ADCINB3 input ADC Group B, channel 3 input.
32 ADCINB4 input ADC Group B channel 4 input, shared with COMP2B comparator input and AIO12 digital I/O.
33 ADCINB5 input ADC Group B, channel 5 input.
34 ADCINB6 input ADC Group B channel 6 input, shared with COMP3B comparator input and AIO14 digital I/O.
35 ADCINB7 input ADC Group B, channel 7 input.
36 VSS power_in Digital ground pin.
37 VDD power_in CPU and logic digital power pin; 1.2-µF capacitor to ground when using internal VREG.
38 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
39 GPIO25 bidirectional General-purpose I/O 25 with mux options ECAP2, EQEP2B and SPISOMIB.
40 GPIO31 bidirectional General-purpose I/O 31 with mux options CANTXA, EQEP2S and EPWM8A.
41 GPIO30 bidirectional General-purpose I/O 30 with mux options CANRXA, EQEP2I and EPWM7A.
42 GPIO50 bidirectional General-purpose I/O 50 with mux options EQEP1A, MDXA and TZ1.
43 GPIO29 bidirectional General-purpose I/O 29 with mux options SCITXDA, SCLA (I2C clock, open-drain) and TZ3.
44 GPIO12 bidirectional General-purpose I/O 12 with mux options TZ1, SCITXDA and SPISIMOB.
45 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
46 VDD3VFL power_in 3.3-V Flash core power pin; must be connected to 3.3 V at all times.
47 VSS power_in Digital ground pin.
48 GPIO51 bidirectional General-purpose I/O 51 with mux options EQEP1B, MDRA and TZ2.
49 GPIO9 bidirectional General-purpose I/O 9 with mux options EPWM5B, SCITXDB and ECAP3.
50 GPIO28 bidirectional General-purpose I/O 28 with mux options SCIRXDA, SDAA (I2C data, open-drain) and TZ2.
51 GPIO18 bidirectional General-purpose I/O 18 with mux options SPICLKA, SCITXDB and XCLKOUT.
52 GPIO17 bidirectional General-purpose I/O 17 with mux options SPISOMIA and TZ3.
53 GPIO52 bidirectional General-purpose I/O 52 with mux options EQEP1S, MCLKXA and TZ3.
54 GPIO8 bidirectional General-purpose I/O 8 with mux options EPWM5A and ADCSOCAO.
55 GPIO16 bidirectional General-purpose I/O 16 with mux options SPISIMOA and TZ2.
56 GPIO44 bidirectional General-purpose I/O 44 with mux options MFSRA, SCIRXDB and EPWM7B.
57 GPIO7 bidirectional General-purpose I/O 7 with mux options EPWM4B, SCIRXDA and ECAP2.
58 GPIO6 bidirectional General-purpose I/O 6 with mux options EPWM4A, EPWMSYNCI and EPWMSYNCO.
59 X2 output On-chip crystal-oscillator output; connect crystal or resonator across X1 and X2, leave unconnected if unused.
60 X1 input On-chip 1.8-V crystal-oscillator input; connect crystal or resonator across X1 and X2, tie to GND if not used.
61 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
62 VSS power_in Digital ground pin.
63 VDD power_in CPU and logic digital power pin; 1.2-µF capacitor to ground when using internal VREG.
64 GPIO19 bidirectional General-purpose I/O 19 with mux options XCLKIN, SPISTEA, SCIRXDB and ECAP1; may glitch during power up with on-chip VREG.
65 GPIO53 bidirectional General-purpose I/O 53 with mux options EQEP1I and MFSXA.
66 GPIO39 bidirectional General-purpose I/O 39; other mux functions are reserved.
67 GPIO38 bidirectional General-purpose I/O 38 with mux options XCLKIN and TCK (JTAG test clock, internal pullup).
68 GPIO34 bidirectional General-purpose I/O 34 with mux options COMP2OUT and COMP3OUT.
69 GPIO54 bidirectional General-purpose I/O 54 with mux options SPISIMOA, EQEP2A and HRCAP1.
70 GPIO37 bidirectional General-purpose I/O 37 with mux option TDO (JTAG scan out, 8-mA drive).
71 GPIO35 bidirectional General-purpose I/O 35 with mux option TDI (JTAG test data input, internal pullup).
72 GPIO36 bidirectional General-purpose I/O 36 with mux option TMS (JTAG test-mode select, internal pullup).
73 GPIO11 bidirectional General-purpose I/O 11 with mux options EPWM6B, SCIRXDB and ECAP1.
74 GPIO10 bidirectional General-purpose I/O 10 with mux options EPWM6A and ADCSOCBO.
75 GPIO55 bidirectional General-purpose I/O 55 with mux options SPISOMIA, EQEP2B and HRCAP2.
76 GPIO41 bidirectional General-purpose I/O 41 with mux options EPWM7B and SCIRXDB.
77 GPIO27 bidirectional General-purpose I/O 27 with mux options HRCAP2, EQEP2S, SPISTEB and USB0DM; may glitch during power up with on-chip VREG.
78 GPIO26 bidirectional General-purpose I/O 26 with mux options ECAP3, EQEP2I, SPICLKB and USB0DP; may glitch during power up with on-chip VREG.
79 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
80 VSS power_in Digital ground pin.
81 VDD power_in CPU and logic digital power pin; 1.2-µF capacitor to ground when using internal VREG.
82 GPIO40 bidirectional General-purpose I/O 40 with mux options EPWM7A and SCITXDB.
83 GPIO3 bidirectional General-purpose I/O 3 with mux options EPWM2B, SPISOMIA and COMP2OUT.
84 GPIO2 bidirectional General-purpose I/O 2 with mux option EPWM2A (HRPWM channel).
85 GPIO56 bidirectional General-purpose I/O 56 with mux options SPICLKA, EQEP2I and HRCAP3.
86 GPIO1 bidirectional General-purpose I/O 1 with mux options EPWM1B and COMP1OUT.
87 GPIO0 bidirectional General-purpose I/O 0 with mux option EPWM1A (HRPWM channel).
88 GPIO15 bidirectional General-purpose I/O 15 with mux options ECAP2, SCIRXDB and SPISTEB.
89 GPIO57 bidirectional General-purpose I/O 57 with mux options SPISTEA, EQEP2S and HRCAP4.
90 VREGENZ input Internal VREG enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or to VDDIO to disable it and use an external 1.8-V supply.
91 VDD power_in CPU and logic digital power pin; 1.2-µF capacitor to ground when using internal VREG.
92 VSS power_in Digital ground pin.
93 VDDIO power_in Digital I/O buffers power pin; place a decoupling capacitor on each pin.
94 GPIO58 bidirectional General-purpose I/O 58 with mux options MCLKRA, SCITXDB and EPWM7A.
95 GPIO13 bidirectional General-purpose I/O 13 with mux options TZ2 and SPISOMIB.
96 GPIO14 bidirectional General-purpose I/O 14 with mux options TZ3, SCITXDB and SPICLKB.
97 GPIO24 bidirectional General-purpose I/O 24 with mux options ECAP1, EQEP2A and SPISIMOB.
98 GPIO22 bidirectional General-purpose I/O 22 with mux options EQEP1S, MCLKXA and SCITXDB.
99 GPIO32 bidirectional General-purpose I/O 32 with mux options SDAA (I2C data, open-drain), EPWMSYNCI and ADCSOCAO.
100 GPIO33 bidirectional General-purpose I/O 33 with mux options SCLA (I2C clock, open-drain), EPWMSYNCO and ADCSOCBO.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28062UPZT
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28062upzt-etched.step / tms320f28062upzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28062upzt.step / tms320f28062upzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF