component
TMS320F28062PZT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28062PZT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
TMS320F28062PZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO42 | bidirectional | General-purpose I/O 42 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EPWM8A (Enhanced PWM8 output A / HRPWM channel), TZ1 (Trip zone input 1), and COMP1OUT (direct output of Comparator 1). |
| 2 | GPIO23 | bidirectional | General-purpose I/O 23, default GPIO; alternate functions EQEP1I (Enhanced QEP1 index I/O), MFSXA (McBSP transmit frame sync I/O), and SCIRXDB (SCI-B receive data). |
| 3 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF (typical, higher values allowed) capacitor between each VDD pin and ground. |
| 4 | VSS | power_in | Digital ground pin. |
| 5 | VDDIO | power_in | Digital I/O buffer power pin, single supply source when VREG is enabled; place a decoupling capacitor sized per the system voltage-regulation solution. |
| 6 | GPIO20 | bidirectional | General-purpose I/O 20, default GPIO; alternate functions EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data output), and COMP1OUT (direct output of Comparator 1). |
| 7 | GPIO21 | bidirectional | General-purpose I/O 21, default GPIO; alternate functions EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data input), and COMP2OUT (direct output of Comparator 2). |
| 8 | GPIO43 | bidirectional | General-purpose I/O 43 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EPWM8B (Enhanced PWM8 output B), TZ2 (Trip zone input 2), and COMP2OUT (direct output of Comparator 2). |
| 9 | GPIO4 | bidirectional | General-purpose I/O 4, default GPIO; alternate function EPWM3A, Enhanced PWM3 output A / HRPWM channel. |
| 10 | GPIO5 | bidirectional | General-purpose I/O 5, default GPIO; alternate functions EPWM3B (Enhanced PWM3 output B), SPISIMOA (SPI-A slave in/master out), and ECAP1 (Enhanced Capture 1 I/O). |
| 11 | XRS | bidirectional | Device reset input / watchdog reset open-drain output with internal pullup; driven low during POR/BOR and for 512 OSCCLK cycles during a watchdog reset. Use an external 2.2-kΩ to 10-kΩ resistor to VDDIO and an optional ≤100-nF filter capacitor to VSS. |
| 12 | TRST | input | JTAG test reset input with internal pulldown; must be held low during normal device operation (active-high enables scan/test mode). TI recommends an external pulldown resistor (~2.2 kΩ typical, sized per debug-pod drive strength). |
| 13 | VDDIO | power_in | Digital I/O buffer power pin, single supply source when VREG is enabled; place a decoupling capacitor sized per the system voltage-regulation solution. |
| 14 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF (typical, higher values allowed) capacitor between each VDD pin and ground. |
| 15 | VSS | power_in | Digital ground pin. |
| 16 | ADCINA7 | input | ADC Group A, Channel 7 analog input. |
| 17 | ADCINA6 | bidirectional | ADC Group A, Channel 6 input; alternate functions Comparator 3 input A (COMP3A) and digital AIO6. |
| 18 | ADCINA5 | input | ADC Group A, Channel 5 analog input. |
| 19 | ADCINA4 | bidirectional | ADC Group A, Channel 4 input; alternate functions Comparator 2 input A (COMP2A) and digital AIO4. |
| 20 | ADCINA3 | input | ADC Group A, Channel 3 analog input. |
| 21 | ADCINA2 | bidirectional | ADC Group A, Channel 2 input; alternate functions Comparator 1 input A (COMP1A) and digital AIO2. |
| 22 | ADCINA1 | input | ADC Group A, Channel 1 analog input. |
| 23 | ADCINA0 | input | ADC Group A, Channel 0 analog input (a separate pin from VREFHI on the 100-pin PZ/PZP package). |
| 24 | VREFHI | passive | ADC external reference-high input, used only when the ADC is in external reference mode; must not exceed VDDA. |
| 25 | VDDA | power_in | Analog power pin; decouple with a 2.2-µF capacitor (typical) close to the pin. |
| 26 | VSSA | power_in | Analog ground pin. |
| 27 | VREFLO | passive | ADC external reference-low input, used only when the ADC is in external reference mode. |
| 28 | ADCINB0 | input | ADC Group B, Channel 0 analog input. |
| 29 | ADCINB1 | input | ADC Group B, Channel 1 analog input. |
| 30 | ADCINB2 | bidirectional | ADC Group B, Channel 2 input; alternate functions Comparator 1 input B (COMP1B) and digital AIO10. |
| 31 | ADCINB3 | input | ADC Group B, Channel 3 analog input. |
| 32 | ADCINB4 | bidirectional | ADC Group B, Channel 4 input; alternate functions Comparator 2 input B (COMP2B) and digital AIO12. |
| 33 | ADCINB5 | input | ADC Group B, Channel 5 analog input. |
| 34 | ADCINB6 | bidirectional | ADC Group B, Channel 6 input; alternate functions Comparator 3 input B (COMP3B) and digital AIO14. |
| 35 | ADCINB7 | input | ADC Group B, Channel 7 analog input. |
| 36 | VSS | power_in | Digital ground pin. |
| 37 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF (typical, higher values allowed) capacitor between each VDD pin and ground. |
| 38 | VDDIO | power_in | Digital I/O buffer power pin, single supply source when VREG is enabled; place a decoupling capacitor sized per the system voltage-regulation solution. |
| 39 | GPIO25 | bidirectional | General-purpose I/O 25, default GPIO; alternate functions ECAP2 (Enhanced Capture 2 I/O), EQEP2B (Enhanced QEP2 input B), and SPISOMIB (SPI-B slave out/master in). |
| 40 | GPIO31 | bidirectional | General-purpose I/O 31, default GPIO; alternate functions CANTXA (CAN transmit), EQEP2S (Enhanced QEP2 strobe), and EPWM8A (Enhanced PWM8 output A / HRPWM channel). |
| 41 | GPIO30 | bidirectional | General-purpose I/O 30, default GPIO; alternate functions CANRXA (CAN receive), EQEP2I (Enhanced QEP2 index), and EPWM7A (Enhanced PWM7 output A / HRPWM channel). |
| 42 | GPIO50 | bidirectional | General-purpose I/O 50 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EQEP1A (Enhanced QEP1 input A), MDXA (McBSP transmit serial data output), and TZ1 (Trip zone input 1). |
| 43 | GPIO29 | bidirectional | General-purpose I/O 29, default GPIO; alternate functions SCITXDA (SCI-A transmit data), SCLA (I2C clock, open-drain bidirectional), and TZ3 (Trip zone input 3). |
| 44 | GPIO12 | bidirectional | General-purpose I/O 12, default GPIO; alternate functions TZ1 (Trip Zone input 1), SCITXDA (SCI-A transmit data), and SPISIMOB (SPI-B slave in/master out). |
| 45 | TEST2 | unconnected | Test pin reserved for TI; must be left unconnected. |
| 46 | VDD3VFL | power_in | 3.3-V Flash core power pin; must be connected to 3.3 V at all times. |
| 47 | VSS | power_in | Digital ground pin. |
| 48 | GPIO51 | bidirectional | General-purpose I/O 51 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EQEP1B (Enhanced QEP1 input B), MDRA (McBSP receive serial data input), and TZ2 (Trip zone input 2). |
| 49 | GPIO9 | bidirectional | General-purpose I/O 9, default GPIO; alternate functions EPWM5B (Enhanced PWM5 output B), SCITXDB (SCI-B transmit data), and ECAP3 (Enhanced Capture 3 I/O). |
| 50 | GPIO28 | bidirectional | General-purpose I/O 28, default GPIO; alternate functions SCIRXDA (SCI-A receive data), SDAA (I2C data, open-drain bidirectional), and TZ2 (Trip zone input 2). |
| 51 | GPIO18 | bidirectional | General-purpose I/O 18, default GPIO; alternate functions SPICLKA (SPI-A clock I/O), SCITXDB (SCI-B transmit data), and XCLKOUT (buffered SYSCLKOUT output, default /4 at reset, ratio set by XCLKOUTDIV). |
| 52 | GPIO17 | bidirectional | General-purpose I/O 17, default GPIO; alternate functions SPISOMIA (SPI-A slave out/master in) and TZ3 (Trip zone input 3). |
| 53 | GPIO52 | bidirectional | General-purpose I/O 52 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), and TZ3 (Trip zone input 3). |
| 54 | GPIO8 | bidirectional | General-purpose I/O 8, default GPIO; alternate functions EPWM5A (Enhanced PWM5 output A / HRPWM channel) and ADCSOCAO (ADC start-of-conversion A output). |
| 55 | GPIO16 | bidirectional | General-purpose I/O 16, default GPIO; alternate functions SPISIMOA (SPI-A slave in/master out) and TZ2 (Trip Zone input 2). |
| 56 | GPIO44 | bidirectional | General-purpose I/O 44 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions MFSRA (McBSP receive frame sync I/O), SCIRXDB (SCI-B receive data), and EPWM7B (Enhanced PWM7 output B). |
| 57 | GPIO7 | bidirectional | General-purpose I/O 7, default GPIO; alternate functions EPWM4B (Enhanced PWM4 output B), SCIRXDA (SCI-A receive data), and ECAP2 (Enhanced Capture 2 I/O). |
| 58 | GPIO6 | bidirectional | General-purpose I/O 6, default GPIO; alternate functions EPWM4A (Enhanced PWM4 output A / HRPWM channel), EPWMSYNCI (external ePWM sync pulse input), and EPWMSYNCO (external ePWM sync pulse output). |
| 59 | X2 | output | On-chip crystal-oscillator output; a quartz crystal or ceramic resonator must be connected across X1/X2, or leave unconnected if unused. |
| 60 | X1 | input | On-chip 1.8-V crystal-oscillator input; a quartz crystal or ceramic resonator must be connected across X1/X2, or tie to GND if unused (with on-chip oscillator disabled via CLKCTL bit 13 when using external XCLKIN). |
| 61 | VDDIO | power_in | Digital I/O buffer power pin, single supply source when VREG is enabled; place a decoupling capacitor sized per the system voltage-regulation solution. |
| 62 | VSS | power_in | Digital ground pin. |
| 63 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF (typical, higher values allowed) capacitor between each VDD pin and ground. |
| 64 | GPIO19 | bidirectional | General-purpose I/O 19, default GPIO; alternate functions XCLKIN (external oscillator input, path not gated by pin mux), SPISTEA (SPI-A slave transmit enable I/O), SCIRXDB (SCI-B receive data), and ECAP1 (Enhanced Capture 1 I/O). |
| 65 | GPIO53 | bidirectional | General-purpose I/O 53 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EQEP1I (Enhanced QEP1 index I/O) and MFSXA (McBSP transmit frame sync I/O). |
| 66 | GPIO39 | bidirectional | General-purpose I/O 39, default GPIO; no alternate peripheral function (reserved). |
| 67 | GPIO38 | bidirectional | General-purpose I/O 38, default GPIO; alternate functions XCLKIN (external oscillator input, path not gated by pin mux) and TCK (JTAG test clock with internal pullup). |
| 68 | GPIO34 | bidirectional | General-purpose I/O 34, default GPIO; alternate functions COMP2OUT (direct output of Comparator 2) and COMP3OUT (direct output of Comparator 3). |
| 69 | GPIO54 | bidirectional | General-purpose I/O 54 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions SPISIMOA (SPI-A slave in/master out), EQEP2A (Enhanced QEP2 input A), and HRCAP1 (High-Resolution Input Capture 1). |
| 70 | GPIO37 | bidirectional | General-purpose I/O 37, default GPIO; alternate function TDO, JTAG scan-out test data output (8-mA drive), shifted out on the falling edge of TCK. |
| 71 | GPIO35 | bidirectional | General-purpose I/O 35, default GPIO; alternate function TDI, JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK. |
| 72 | GPIO36 | bidirectional | General-purpose I/O 36, default GPIO; alternate function TMS, JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK. |
| 73 | GPIO11 | bidirectional | General-purpose I/O 11, default GPIO; alternate functions EPWM6B (Enhanced PWM6 output B), SCIRXDB (SCI-B receive data), and ECAP1 (Enhanced Capture 1 I/O). |
| 74 | GPIO10 | bidirectional | General-purpose I/O 10, default GPIO; alternate functions EPWM6A (Enhanced PWM6 output A / HRPWM channel) and ADCSOCBO (ADC start-of-conversion B output). |
| 75 | GPIO55 | bidirectional | General-purpose I/O 55 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions SPISOMIA (SPI-A slave out/master in), EQEP2B (Enhanced QEP2 input B), and HRCAP2 (High-Resolution Input Capture 2). |
| 76 | GPIO41 | bidirectional | General-purpose I/O 41 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EPWM7B (Enhanced PWM7 output B) and SCIRXDB (SCI-B receive data). |
| 77 | GPIO27 | bidirectional | General-purpose I/O 27, default GPIO; alternate functions HRCAP2 (High-Resolution Input Capture 2), EQEP2S (Enhanced QEP2 strobe), SPISTEB (SPI-B slave transmit enable I/O), and USB0DM (USB negative differential signal, enabled via USBIOEN bit). |
| 78 | GPIO26 | bidirectional | General-purpose I/O 26, default GPIO; alternate functions ECAP3 (Enhanced Capture 3 I/O), EQEP2I (Enhanced QEP2 index), SPICLKB (SPI-B clock I/O), and USB0DP (USB positive differential signal, enabled via USBIOEN bit). |
| 79 | VDDIO | power_in | Digital I/O buffer power pin, single supply source when VREG is enabled; place a decoupling capacitor sized per the system voltage-regulation solution. |
| 80 | VSS | power_in | Digital ground pin. |
| 81 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF (typical, higher values allowed) capacitor between each VDD pin and ground. |
| 82 | GPIO40 | bidirectional | General-purpose I/O 40 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions EPWM7A (Enhanced PWM7 output A / HRPWM channel) and SCITXDB (SCI-B transmit data). |
| 83 | GPIO3 | bidirectional | General-purpose I/O 3, default GPIO; alternate functions EPWM2B (Enhanced PWM2 output B), SPISOMIA (SPI-A slave out/master in), and COMP2OUT (direct output of Comparator 2). |
| 84 | GPIO2 | bidirectional | General-purpose I/O 2, default GPIO; alternate function EPWM2A, Enhanced PWM2 output A / HRPWM channel. |
| 85 | GPIO56 | bidirectional | General-purpose I/O 56 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions SPICLKA (SPI-A clock I/O), EQEP2I (Enhanced QEP2 index I/O), and HRCAP3 (High-Resolution Input Capture 3). |
| 86 | GPIO1 | bidirectional | General-purpose I/O 1, default GPIO; alternate functions EPWM1B (Enhanced PWM1 output B) and COMP1OUT (direct output of Comparator 1). |
| 87 | GPIO0 | bidirectional | General-purpose I/O 0, default GPIO; alternate function EPWM1A, Enhanced PWM1 output A / HRPWM channel. |
| 88 | GPIO15 | bidirectional | General-purpose I/O 15, default GPIO; alternate functions ECAP2 (Enhanced Capture 2 I/O), SCIRXDB (SCI-B receive data), and SPISTEB (SPI-B slave transmit enable I/O). |
| 89 | GPIO57 | bidirectional | General-purpose I/O 57 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions SPISTEA (SPI-A slave transmit enable I/O), EQEP2S (Enhanced QEP2 strobe I/O), and HRCAP4 (High-Resolution Input Capture 4). |
| 90 | VREGENZ | input | Internal voltage regulator (VREG) enable, internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or tie to VDDIO to disable it and use an external 1.8-V supply. |
| 91 | VDD | power_in | CPU and logic digital power pin; when using the internal VREG, place a 1.2-µF (typical, higher values allowed) capacitor between each VDD pin and ground. |
| 92 | VSS | power_in | Digital ground pin. |
| 93 | VDDIO | power_in | Digital I/O buffer power pin, single supply source when VREG is enabled; place a decoupling capacitor sized per the system voltage-regulation solution. |
| 94 | GPIO58 | bidirectional | General-purpose I/O 58 (present only on the PZ/PZP 100-pin package), default GPIO; alternate functions MCLKRA (McBSP receive clock I/O), SCITXDB (SCI-B transmit data), and EPWM7A (Enhanced PWM7 output A / HRPWM channel). |
| 95 | GPIO13 | bidirectional | General-purpose I/O 13, default GPIO; alternate functions TZ2 (Trip Zone input 2) and SPISOMIB (SPI-B slave out/master in). |
| 96 | GPIO14 | bidirectional | General-purpose I/O 14, default GPIO; alternate functions TZ3 (Trip zone input 3), SCITXDB (SCI-B transmit data), and SPICLKB (SPI-B clock I/O). |
| 97 | GPIO24 | bidirectional | General-purpose I/O 24, default GPIO; alternate functions ECAP1 (Enhanced Capture 1 I/O), EQEP2A (Enhanced QEP2 input A), and SPISIMOB (SPI-B slave in/master out). |
| 98 | GPIO22 | bidirectional | General-purpose I/O 22, default GPIO; alternate functions EQEP1S (Enhanced QEP1 strobe I/O), MCLKXA (McBSP transmit clock I/O), and SCITXDB (SCI-B transmit data). |
| 99 | GPIO32 | bidirectional | General-purpose I/O 32, default GPIO; alternate functions SDAA (I2C data, open-drain bidirectional), EPWMSYNCI (ePWM external sync pulse input), and ADCSOCAO (ADC start-of-conversion A output). |
| 100 | GPIO33 | bidirectional | General-purpose I/O 33, default GPIO; alternate functions SCLA (I2C clock, open-drain bidirectional), EPWMSYNCO (ePWM external sync pulse output), and ADCSOCBO (ADC start-of-conversion B output). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
TMS320F28062PZT - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
tms320f28062pzt-etched.step/tms320f28062pzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28062pzt.step/tms320f28062pzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (206 pp, sha256
3033efed856fc72a, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).