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TMS320F28055PNT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28055PNT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28055PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/SCITXDB bidirectional General-purpose I/O 22 (default GPIO) with alternate functions EQEP1S (I/O) and SCITXDB (O); inputs are not 5-V tolerant and the internal pullup is enabled at reset.
2 GPIO32/SDAA/EPWMSYNCI/EQEP1S bidirectional General-purpose I/O 32 (default GPIO) with alternate functions SDAA (I2C data, open-drain), EPWMSYNCI (input) and EQEP1S (I/O); inputs are not 5-V tolerant.
3 GPIO33/SCLA/EPWMSYNCO/EQEP1I bidirectional General-purpose I/O 33 (default GPIO) with alternate functions SCLA (I2C clock, open-drain), EPWMSYNCO (output) and EQEP1I (I/O); inputs are not 5-V tolerant.
4 GPIO24/ECAP1/EPWM7A bidirectional General-purpose I/O 24 with internal pullup enabled by default, alternate functions ECAP1 (I/O) and EPWM7A (output); inputs are not 5-V tolerant.
5 GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT bidirectional General-purpose I/O 42 with internal pullup enabled by default, alternate functions EPWM7B, SCITXDC and CTRIPM1OUT (outputs); inputs are not 5-V tolerant.
6 VDD power_in CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used).
7 VSS power_in Digital ground pin.
8 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is required, a capacitor to VSS must be 100 nF or smaller, and external drivers must be open-drain.
9 TRST input JTAG test reset input with internal pulldown that must be kept low during normal device operation and requires an external pulldown (2.2 kΩ generally adequate).
10 ADCINA5 input ADC Group A channel 5 analog input (ADC full-scale 0 V to 3.3 V).
11 ADCINA4 input ADC Group A channel 4 analog input (ADC full-scale 0 V to 3.3 V).
12 ADCINA3 (op-amp) input ADC Group A channel 3 analog input, labelled as op-amp channel A3 in the datasheet; ground reference is M1GND.
13 ADCINA2 input ADC Group A channel 2 analog input (ADC full-scale 0 V to 3.3 V).
14 ADCINA1 (op-amp) input ADC Group A channel 1 analog input, labelled as op-amp channel A1 in the datasheet; ground reference is M1GND.
15 M1GND power_in Ground pin for amplifier channels A1, A3 and B1.
16 ADCINB2 input ADC Group B channel 2 analog input (ADC full-scale 0 V to 3.3 V).
17 ADCINB1 (op-amp) input ADC Group B channel 1 analog input, labelled as op-amp channel B1 in the datasheet; ground reference is M1GND.
18 ADCINA0/VREFOUT input ADC Group A channel 0 analog input, shared with VREFOUT, the voltage reference output from the buffered DAC.
19 VREFHI input ADC external reference input, used in ADC external reference mode and as the VREFOUT reference.
20 VDDA power_in Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin.
21 VSSA power_in Analog ground pin.
22 VREFLO input ADC low reference, always tied to ground.
23 ADCINA6 (op-amp) input ADC Group A channel 6 analog input, labelled as op-amp channel A6 in the datasheet; ground reference is M2GND.
24 ADCINA7 input ADC Group A channel 7 analog input (ADC full-scale 0 V to 3.3 V).
25 ADCINB3 input ADC Group B channel 3 analog input (ADC full-scale 0 V to 3.3 V).
26 ADCINB4 (op-amp) input ADC Group B channel 4 analog input, labelled as op-amp channel B4 in the datasheet; ground reference is M2GND.
27 M2GND power_in Ground pin for amplifier channels A6, B4 and B6.
28 ADCINB5 input ADC Group B channel 5 analog input (ADC full-scale 0 V to 3.3 V).
29 ADCINB6 (op-amp) input ADC Group B channel 6 analog input, labelled as op-amp channel B6 in the datasheet; ground reference is M2GND.
30 ADCINB0 input ADC Group B channel 0 analog input (ADC full-scale 0 V to 3.3 V).
31 ADCINB7 (op-amp) input ADC Group B channel 7 analog input, labelled as op-amp channel B7 in the datasheet; ground reference is PFCGND.
32 PFCGND power_in Ground pin for amplifier channel B7.
33 GPIO27/SCITXDC bidirectional General-purpose I/O 27 (default GPIO) with alternate function SCITXDC (SCI-C transmit, output); inputs are not 5-V tolerant.
34 GPIO31/CANTXA/SCITXDB/EPWM7B bidirectional General-purpose I/O 31 with internal pullup enabled by default, alternate functions CANTXA, SCITXDB and EPWM7B (outputs); inputs are not 5-V tolerant.
35 GPIO30/CANRXA/SCIRXDB/EPWM7A bidirectional General-purpose I/O 30 with internal pullup enabled by default, alternate functions CANRXA (input), SCIRXDB (input) and EPWM7A (output); inputs are not 5-V tolerant.
36 GPIO9/EPWM5B/SCITXDB bidirectional General-purpose I/O 9 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM5B and SCITXDB (outputs); inputs are not 5-V tolerant.
37 VSS power_in Digital ground pin.
38 VDDIO power_in Digital I/O buffer and flash memory power pin; the single supply source when VREG is enabled, with a decoupling capacitor on each pin (value set by the system voltage regulation solution).
39 TEST2 bidirectional Test pin reserved for TI; must be left unconnected.
40 GPIO26/SCIRXDC bidirectional General-purpose I/O 26 (default GPIO) with alternate function SCIRXDC (SCI-C receive, input); inputs are not 5-V tolerant.
41 GPIO29 bidirectional General-purpose I/O 29 (default GPIO) with alternate functions SCITXDA (output), SCLA (I2C clock, open-drain), TZ3 (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant.
42 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O 28 (default GPIO) with alternate functions SCIRXDA (input), SDAA (I2C data, open-drain) and TZ2 (input); inputs are not 5-V tolerant.
43 GPIO18/SPICLKA/SCITXDB/XCLKOUT bidirectional General-purpose I/O 18 (default GPIO) with alternate functions SPICLKA (I/O), SCITXDB (output) and XCLKOUT (output, SYSCLKOUT/4 at reset, disabled when XCLKOUTDIV = 3); inputs are not 5-V tolerant.
44 GPIO17 bidirectional General-purpose I/O 17 (default GPIO) with alternate functions SPISOMIA (I/O), EQEP1I (I/O), TZ3 (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant.
45 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O 8 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM5A and ADCSOCAO (outputs); inputs are not 5-V tolerant.
46 GPIO25 bidirectional General-purpose I/O 25 (default GPIO) with no peripheral alternate functions listed; inputs are not 5-V tolerant.
47 GPIO16/SPISIMOA/EQEP1S/TZ2 bidirectional General-purpose I/O 16 (default GPIO) with alternate functions SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (input); inputs are not 5-V tolerant.
48 GPIO12 bidirectional General-purpose I/O 12 (default GPIO) with alternate functions TZ1 (input), CTRIPM1OUT (output) and SCITXDA (output); inputs are not 5-V tolerant.
49 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O 7 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM4B (output) and SCIRXDA (input); inputs are not 5-V tolerant.
50 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM4A (output), EPWMSYNCI (input) and EPWMSYNCO (output); inputs are not 5-V tolerant.
51 X2 output On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 is left unconnected if not used.
52 X1 input On-chip 1.8-V crystal oscillator input; a crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used.
53 VSS power_in Digital ground pin.
54 VDD power_in CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used).
55 GPIO19 bidirectional General-purpose I/O 19 (default GPIO) with alternate functions XCLKIN (external 3.3-V oscillator input, not gated by the mux), SPISTEA (I/O), SCIRXDB (input) and ECAP1 (I/O); can glitch at power-up when the internal VREG is used.
56 GPIO39/SCIRXDC/CTRIPPFCOUT bidirectional General-purpose I/O 39 (default GPIO) with alternate functions SCIRXDC (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant.
57 GPIO38 bidirectional General-purpose I/O 38 (default XCLKIN selection) with JTAG TCK function (input, internal pullup); can glitch at power-up when the internal VREG is used, and the XCLKIN path must not be enabled while TCK is in use during debug.
58 GPIO37/TDO tri_state General-purpose I/O 37 with JTAG scan data output TDO (O/Z, 8 mA drive), shifted out on the falling edge of TCK; can glitch at power-up when the internal VREG is used.
59 GPIO35/TDI bidirectional General-purpose I/O 35 with JTAG test data input TDI (internal pullup), clocked into the selected register on the rising edge of TCK; does not have a glitch-free output at power-up.
60 GPIO36/TMS bidirectional General-purpose I/O 36 with JTAG test-mode select TMS (internal pullup), clocked into the TAP controller on the rising edge of TCK; does not have a glitch-free output at power-up.
61 GPIO11/EPWM6B/SCIRXDB bidirectional General-purpose I/O 11 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM6B (output) and SCIRXDB (input); inputs are not 5-V tolerant.
62 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O 5 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM3B (output), SPISIMOA (I/O) and ECAP1 (I/O); inputs are not 5-V tolerant.
63 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM3A (output); inputs are not 5-V tolerant.
64 GPIO40/EPWM7A bidirectional General-purpose I/O 40 with internal pullup enabled by default and alternate function EPWM7A (output); inputs are not 5-V tolerant.
65 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O 10 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM6A and ADCSOCBO (outputs); inputs are not 5-V tolerant.
66 GPIO3/EPWM2B/SPISOMIA bidirectional General-purpose I/O 3 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM2B (output) and SPISOMIA (I/O); inputs are not 5-V tolerant.
67 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM2A (output); inputs are not 5-V tolerant.
68 GPIO1/EPWM1B/CTRIPM1OUT bidirectional General-purpose I/O 1 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM1B and CTRIPM1OUT (outputs); inputs are not 5-V tolerant.
69 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM1A (output); inputs are not 5-V tolerant.
70 VDDIO power_in Digital I/O buffer and flash memory power pin; the single supply source when VREG is enabled, with a decoupling capacitor on each pin (value set by the system voltage regulation solution).
71 VREGENZ input Internal voltage regulator enable with internal pulldown; tie directly to VSS to enable the internal 1.8-V VREG, or tie directly to VDDIO to disable it and use an external 1.8-V supply.
72 VSS power_in Digital ground pin.
73 VDD power_in CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used).
74 GPIO34/CTRIPPFCOUT bidirectional General-purpose I/O 34 with alternate function CTRIPPFCOUT (output); this pin is not glitch-free at power-up (GPIO34 to GPIO38 and GPIO19 do not have glitch-free I/Os).
75 GPIO15/TZ1/CTRIPM1OUT/SCIRXDB bidirectional General-purpose I/O 15 (default GPIO) with alternate functions TZ1 (input), CTRIPM1OUT (output) and SCIRXDB (input); inputs are not 5-V tolerant.
76 GPIO13/TZ2 bidirectional General-purpose I/O 13 (default GPIO) with alternate function TZ2 (trip zone input 2); inputs are not 5-V tolerant.
77 GPIO14/TZ3/CTRIPPFCOUT/SCITXDB bidirectional General-purpose I/O 14 (default GPIO) with alternate functions TZ3 (input), CTRIPPFCOUT (output) and SCITXDB (output); inputs are not 5-V tolerant.
78 GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT bidirectional General-purpose I/O 20 with internal pullup enabled by default, alternate functions EQEP1A (input), EPWM7A and CTRIPM1OUT (outputs); inputs are not 5-V tolerant.
79 GPIO21/EQEP1B/EPWM7B bidirectional General-purpose I/O 21 with internal pullup enabled by default, alternate functions EQEP1B (input) and EPWM7B (output); inputs are not 5-V tolerant.
80 GPIO23/EQEP1I/SCIRXDB bidirectional General-purpose I/O 23 (default GPIO) with alternate functions EQEP1I (I/O) and SCIRXDB (input); inputs are not 5-V tolerant.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28055PNT
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28055pnt-etched.step / tms320f28055pnt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28055pnt.step / tms320f28055pnt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (159 pp, sha256 aaaaedb6c548633c, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF