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TMS320F28055PNT
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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+117@@ -0,0 +1,117 @@+# TMS320F28055PNT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)++TMS320F28055PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO22/EQEP1S/SCITXDB | bidirectional | General-purpose I/O 22 (default GPIO) with alternate functions EQEP1S (I/O) and SCITXDB (O); inputs are not 5-V tolerant and the internal pullup is enabled at reset. |+| 2 | GPIO32/SDAA/EPWMSYNCI/EQEP1S | bidirectional | General-purpose I/O 32 (default GPIO) with alternate functions SDAA (I2C data, open-drain), EPWMSYNCI (input) and EQEP1S (I/O); inputs are not 5-V tolerant. |+| 3 | GPIO33/SCLA/EPWMSYNCO/EQEP1I | bidirectional | General-purpose I/O 33 (default GPIO) with alternate functions SCLA (I2C clock, open-drain), EPWMSYNCO (output) and EQEP1I (I/O); inputs are not 5-V tolerant. |+| 4 | GPIO24/ECAP1/EPWM7A | bidirectional | General-purpose I/O 24 with internal pullup enabled by default, alternate functions ECAP1 (I/O) and EPWM7A (output); inputs are not 5-V tolerant. |+| 5 | GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT | bidirectional | General-purpose I/O 42 with internal pullup enabled by default, alternate functions EPWM7B, SCITXDC and CTRIPM1OUT (outputs); inputs are not 5-V tolerant. |+| 6 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used). |+| 7 | VSS | power_in | Digital ground pin. |+| 8 | XRS | bidirectional | Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is required, a capacitor to VSS must be 100 nF or smaller, and external drivers must be open-drain. |+| 9 | TRST | input | JTAG test reset input with internal pulldown that must be kept low during normal device operation and requires an external pulldown (2.2 kΩ generally adequate). |+| 10 | ADCINA5 | input | ADC Group A channel 5 analog input (ADC full-scale 0 V to 3.3 V). |+| 11 | ADCINA4 | input | ADC Group A channel 4 analog input (ADC full-scale 0 V to 3.3 V). |+| 12 | ADCINA3 (op-amp) | input | ADC Group A channel 3 analog input, labelled as op-amp channel A3 in the datasheet; ground reference is M1GND. |+| 13 | ADCINA2 | input | ADC Group A channel 2 analog input (ADC full-scale 0 V to 3.3 V). |+| 14 | ADCINA1 (op-amp) | input | ADC Group A channel 1 analog input, labelled as op-amp channel A1 in the datasheet; ground reference is M1GND. |+| 15 | M1GND | power_in | Ground pin for amplifier channels A1, A3 and B1. |+| 16 | ADCINB2 | input | ADC Group B channel 2 analog input (ADC full-scale 0 V to 3.3 V). |+| 17 | ADCINB1 (op-amp) | input | ADC Group B channel 1 analog input, labelled as op-amp channel B1 in the datasheet; ground reference is M1GND. |+| 18 | ADCINA0/VREFOUT | input | ADC Group A channel 0 analog input, shared with VREFOUT, the voltage reference output from the buffered DAC. |+| 19 | VREFHI | input | ADC external reference input, used in ADC external reference mode and as the VREFOUT reference. |+| 20 | VDDA | power_in | Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin. |+| 21 | VSSA | power_in | Analog ground pin. |+| 22 | VREFLO | input | ADC low reference, always tied to ground. |+| 23 | ADCINA6 (op-amp) | input | ADC Group A channel 6 analog input, labelled as op-amp channel A6 in the datasheet; ground reference is M2GND. |+| 24 | ADCINA7 | input | ADC Group A channel 7 analog input (ADC full-scale 0 V to 3.3 V). |+| 25 | ADCINB3 | input | ADC Group B channel 3 analog input (ADC full-scale 0 V to 3.3 V). |+| 26 | ADCINB4 (op-amp) | input | ADC Group B channel 4 analog input, labelled as op-amp channel B4 in the datasheet; ground reference is M2GND. |+| 27 | M2GND | power_in | Ground pin for amplifier channels A6, B4 and B6. |+| 28 | ADCINB5 | input | ADC Group B channel 5 analog input (ADC full-scale 0 V to 3.3 V). |+| 29 | ADCINB6 (op-amp) | input | ADC Group B channel 6 analog input, labelled as op-amp channel B6 in the datasheet; ground reference is M2GND. |+| 30 | ADCINB0 | input | ADC Group B channel 0 analog input (ADC full-scale 0 V to 3.3 V). |+| 31 | ADCINB7 (op-amp) | input | ADC Group B channel 7 analog input, labelled as op-amp channel B7 in the datasheet; ground reference is PFCGND. |+| 32 | PFCGND | power_in | Ground pin for amplifier channel B7. |+| 33 | GPIO27/SCITXDC | bidirectional | General-purpose I/O 27 (default GPIO) with alternate function SCITXDC (SCI-C transmit, output); inputs are not 5-V tolerant. |+| 34 | GPIO31/CANTXA/SCITXDB/EPWM7B | bidirectional | General-purpose I/O 31 with internal pullup enabled by default, alternate functions CANTXA, SCITXDB and EPWM7B (outputs); inputs are not 5-V tolerant. |+| 35 | GPIO30/CANRXA/SCIRXDB/EPWM7A | bidirectional | General-purpose I/O 30 with internal pullup enabled by default, alternate functions CANRXA (input), SCIRXDB (input) and EPWM7A (output); inputs are not 5-V tolerant. |+| 36 | GPIO9/EPWM5B/SCITXDB | bidirectional | General-purpose I/O 9 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM5B and SCITXDB (outputs); inputs are not 5-V tolerant. |+| 37 | VSS | power_in | Digital ground pin. |+| 38 | VDDIO | power_in | Digital I/O buffer and flash memory power pin; the single supply source when VREG is enabled, with a decoupling capacitor on each pin (value set by the system voltage regulation solution). |+| 39 | TEST2 | bidirectional | Test pin reserved for TI; must be left unconnected. |+| 40 | GPIO26/SCIRXDC | bidirectional | General-purpose I/O 26 (default GPIO) with alternate function SCIRXDC (SCI-C receive, input); inputs are not 5-V tolerant. |+| 41 | GPIO29 | bidirectional | General-purpose I/O 29 (default GPIO) with alternate functions SCITXDA (output), SCLA (I2C clock, open-drain), TZ3 (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant. |+| 42 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 (default GPIO) with alternate functions SCIRXDA (input), SDAA (I2C data, open-drain) and TZ2 (input); inputs are not 5-V tolerant. |+| 43 | GPIO18/SPICLKA/SCITXDB/XCLKOUT | bidirectional | General-purpose I/O 18 (default GPIO) with alternate functions SPICLKA (I/O), SCITXDB (output) and XCLKOUT (output, SYSCLKOUT/4 at reset, disabled when XCLKOUTDIV = 3); inputs are not 5-V tolerant. |+| 44 | GPIO17 | bidirectional | General-purpose I/O 17 (default GPIO) with alternate functions SPISOMIA (I/O), EQEP1I (I/O), TZ3 (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant. |+| 45 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | General-purpose I/O 8 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM5A and ADCSOCAO (outputs); inputs are not 5-V tolerant. |+| 46 | GPIO25 | bidirectional | General-purpose I/O 25 (default GPIO) with no peripheral alternate functions listed; inputs are not 5-V tolerant. |+| 47 | GPIO16/SPISIMOA/EQEP1S/TZ2 | bidirectional | General-purpose I/O 16 (default GPIO) with alternate functions SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (input); inputs are not 5-V tolerant. |+| 48 | GPIO12 | bidirectional | General-purpose I/O 12 (default GPIO) with alternate functions TZ1 (input), CTRIPM1OUT (output) and SCITXDA (output); inputs are not 5-V tolerant. |+| 49 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM4B (output) and SCIRXDA (input); inputs are not 5-V tolerant. |+| 50 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM4A (output), EPWMSYNCI (input) and EPWMSYNCO (output); inputs are not 5-V tolerant. |+| 51 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 is left unconnected if not used. |+| 52 | X1 | input | On-chip 1.8-V crystal oscillator input; a crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used. |+| 53 | VSS | power_in | Digital ground pin. |+| 54 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used). |+| 55 | GPIO19 | bidirectional | General-purpose I/O 19 (default GPIO) with alternate functions XCLKIN (external 3.3-V oscillator input, not gated by the mux), SPISTEA (I/O), SCIRXDB (input) and ECAP1 (I/O); can glitch at power-up when the internal VREG is used. |+| 56 | GPIO39/SCIRXDC/CTRIPPFCOUT | bidirectional | General-purpose I/O 39 (default GPIO) with alternate functions SCIRXDC (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant. |+| 57 | GPIO38 | bidirectional | General-purpose I/O 38 (default XCLKIN selection) with JTAG TCK function (input, internal pullup); can glitch at power-up when the internal VREG is used, and the XCLKIN path must not be enabled while TCK is in use during debug. |+| 58 | GPIO37/TDO | tri_state | General-purpose I/O 37 with JTAG scan data output TDO (O/Z, 8 mA drive), shifted out on the falling edge of TCK; can glitch at power-up when the internal VREG is used. |+| 59 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with JTAG test data input TDI (internal pullup), clocked into the selected register on the rising edge of TCK; does not have a glitch-free output at power-up. |+| 60 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with JTAG test-mode select TMS (internal pullup), clocked into the TAP controller on the rising edge of TCK; does not have a glitch-free output at power-up. |+| 61 | GPIO11/EPWM6B/SCIRXDB | bidirectional | General-purpose I/O 11 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM6B (output) and SCIRXDB (input); inputs are not 5-V tolerant. |+| 62 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | General-purpose I/O 5 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM3B (output), SPISIMOA (I/O) and ECAP1 (I/O); inputs are not 5-V tolerant. |+| 63 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM3A (output); inputs are not 5-V tolerant. |+| 64 | GPIO40/EPWM7A | bidirectional | General-purpose I/O 40 with internal pullup enabled by default and alternate function EPWM7A (output); inputs are not 5-V tolerant. |+| 65 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | General-purpose I/O 10 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM6A and ADCSOCBO (outputs); inputs are not 5-V tolerant. |+| 66 | GPIO3/EPWM2B/SPISOMIA | bidirectional | General-purpose I/O 3 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM2B (output) and SPISOMIA (I/O); inputs are not 5-V tolerant. |+| 67 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM2A (output); inputs are not 5-V tolerant. |+| 68 | GPIO1/EPWM1B/CTRIPM1OUT | bidirectional | General-purpose I/O 1 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM1B and CTRIPM1OUT (outputs); inputs are not 5-V tolerant. |+| 69 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM1A (output); inputs are not 5-V tolerant. |+| 70 | VDDIO | power_in | Digital I/O buffer and flash memory power pin; the single supply source when VREG is enabled, with a decoupling capacitor on each pin (value set by the system voltage regulation solution). |+| 71 | VREGENZ | input | Internal voltage regulator enable with internal pulldown; tie directly to VSS to enable the internal 1.8-V VREG, or tie directly to VDDIO to disable it and use an external 1.8-V supply. |+| 72 | VSS | power_in | Digital ground pin. |+| 73 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used). |+| 74 | GPIO34/CTRIPPFCOUT | bidirectional | General-purpose I/O 34 with alternate function CTRIPPFCOUT (output); this pin is not glitch-free at power-up (GPIO34 to GPIO38 and GPIO19 do not have glitch-free I/Os). |+| 75 | GPIO15/TZ1/CTRIPM1OUT/SCIRXDB | bidirectional | General-purpose I/O 15 (default GPIO) with alternate functions TZ1 (input), CTRIPM1OUT (output) and SCIRXDB (input); inputs are not 5-V tolerant. |+| 76 | GPIO13/TZ2 | bidirectional | General-purpose I/O 13 (default GPIO) with alternate function TZ2 (trip zone input 2); inputs are not 5-V tolerant. |+| 77 | GPIO14/TZ3/CTRIPPFCOUT/SCITXDB | bidirectional | General-purpose I/O 14 (default GPIO) with alternate functions TZ3 (input), CTRIPPFCOUT (output) and SCITXDB (output); inputs are not 5-V tolerant. |+| 78 | GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT | bidirectional | General-purpose I/O 20 with internal pullup enabled by default, alternate functions EQEP1A (input), EPWM7A and CTRIPM1OUT (outputs); inputs are not 5-V tolerant. |+| 79 | GPIO21/EQEP1B/EPWM7B | bidirectional | General-purpose I/O 21 with internal pullup enabled by default, alternate functions EQEP1B (input) and EPWM7B (output); inputs are not 5-V tolerant. |+| 80 | GPIO23/EQEP1I/SCIRXDB | bidirectional | General-purpose I/O 23 (default GPIO) with alternate functions EQEP1I (I/O) and SCIRXDB (input); inputs are not 5-V tolerant. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-80(12x12) |+| Category | Embedded Processors & Controllers |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `TMS320F28055PNT`+- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`+- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)+- 3D model files: `tms320f28055pnt-etched.step` / `tms320f28055pnt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28055pnt.step` / `tms320f28055pnt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28054f) (159 pp, sha256 `aaaaedb6c548633c`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28055pnt-datasheet.pdf)
page.jsonadded+631@@ -0,0 +1,631 @@+{+ "slug": "tms320f28055pnt",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28055pnt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28055pnt.kicad_sym",+ "tms320f28055pnt.kicad_mod",+ "tms320f28055pnt.glb",+ "tms320f28055pnt.step",+ "tms320f28055pnt.lbr",+ "docs/hero.png",+ "docs/tms320f28055pnt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320f28055pnt-hero.glb",+ "tms320f28055pnt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320F28055PNT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-80(12x12)",+ "pin_count": 80,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28054f",+ "parts": {+ "symbol": "tms320f28055pnt.kicad_sym",+ "footprint": "tms320f28055pnt.kicad_mod",+ "model_3d": "tms320f28055pnt-hero.glb",+ "model_3d_plain": "tms320f28055pnt.glb",+ "model_3d_step": "tms320f28055pnt-etched.step",+ "model_3d_step_plain": "tms320f28055pnt.step",+ "lbr": "tms320f28055pnt.lbr"+ },+ "distributor_links": {+ "lcsc": "C1339612",+ "digikey": "296-35111-ND",+ "mouser": "595-TMS320F28055PNT"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:48:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-35111-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F28055PNT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO22/EQEP1S/SCITXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 22 (default GPIO) with alternate functions EQEP1S (I/O) and SCITXDB (O); inputs are not 5-V tolerant and the internal pullup is enabled at reset."+ },+ {+ "number": "2",+ "name": "GPIO32/SDAA/EPWMSYNCI/EQEP1S",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 (default GPIO) with alternate functions SDAA (I2C data, open-drain), EPWMSYNCI (input) and EQEP1S (I/O); inputs are not 5-V tolerant."+ },+ {+ "number": "3",+ "name": "GPIO33/SCLA/EPWMSYNCO/EQEP1I",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 (default GPIO) with alternate functions SCLA (I2C clock, open-drain), EPWMSYNCO (output) and EQEP1I (I/O); inputs are not 5-V tolerant."+ },+ {+ "number": "4",+ "name": "GPIO24/ECAP1/EPWM7A",+ "type": "bidirectional",+ "description": "General-purpose I/O 24 with internal pullup enabled by default, alternate functions ECAP1 (I/O) and EPWM7A (output); inputs are not 5-V tolerant."+ },+ {+ "number": "5",+ "name": "GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 42 with internal pullup enabled by default, alternate functions EPWM7B, SCITXDC and CTRIPM1OUT (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "6",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used)."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "8",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is required, a capacitor to VSS must be 100 nF or smaller, and external drivers must be open-drain."+ },+ {+ "number": "9",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset input with internal pulldown that must be kept low during normal device operation and requires an external pulldown (2.2 kΩ generally adequate)."+ },+ {+ "number": "10",+ "name": "ADCINA5",+ "type": "input",+ "description": "ADC Group A channel 5 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "11",+ "name": "ADCINA4",+ "type": "input",+ "description": "ADC Group A channel 4 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "12",+ "name": "ADCINA3 (op-amp)",+ "type": "input",+ "description": "ADC Group A channel 3 analog input, labelled as op-amp channel A3 in the datasheet; ground reference is M1GND."+ },+ {+ "number": "13",+ "name": "ADCINA2",+ "type": "input",+ "description": "ADC Group A channel 2 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "14",+ "name": "ADCINA1 (op-amp)",+ "type": "input",+ "description": "ADC Group A channel 1 analog input, labelled as op-amp channel A1 in the datasheet; ground reference is M1GND."+ },+ {+ "number": "15",+ "name": "M1GND",+ "type": "power_in",+ "description": "Ground pin for amplifier channels A1, A3 and B1."+ },+ {+ "number": "16",+ "name": "ADCINB2",+ "type": "input",+ "description": "ADC Group B channel 2 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "17",+ "name": "ADCINB1 (op-amp)",+ "type": "input",+ "description": "ADC Group B channel 1 analog input, labelled as op-amp channel B1 in the datasheet; ground reference is M1GND."+ },+ {+ "number": "18",+ "name": "ADCINA0/VREFOUT",+ "type": "input",+ "description": "ADC Group A channel 0 analog input, shared with VREFOUT, the voltage reference output from the buffered DAC."+ },+ {+ "number": "19",+ "name": "VREFHI",+ "type": "input",+ "description": "ADC external reference input, used in ADC external reference mode and as the VREFOUT reference."+ },+ {+ "number": "20",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin."+ },+ {+ "number": "21",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "22",+ "name": "VREFLO",+ "type": "input",+ "description": "ADC low reference, always tied to ground."+ },+ {+ "number": "23",+ "name": "ADCINA6 (op-amp)",+ "type": "input",+ "description": "ADC Group A channel 6 analog input, labelled as op-amp channel A6 in the datasheet; ground reference is M2GND."+ },+ {+ "number": "24",+ "name": "ADCINA7",+ "type": "input",+ "description": "ADC Group A channel 7 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "25",+ "name": "ADCINB3",+ "type": "input",+ "description": "ADC Group B channel 3 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "26",+ "name": "ADCINB4 (op-amp)",+ "type": "input",+ "description": "ADC Group B channel 4 analog input, labelled as op-amp channel B4 in the datasheet; ground reference is M2GND."+ },+ {+ "number": "27",+ "name": "M2GND",+ "type": "power_in",+ "description": "Ground pin for amplifier channels A6, B4 and B6."+ },+ {+ "number": "28",+ "name": "ADCINB5",+ "type": "input",+ "description": "ADC Group B channel 5 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "29",+ "name": "ADCINB6 (op-amp)",+ "type": "input",+ "description": "ADC Group B channel 6 analog input, labelled as op-amp channel B6 in the datasheet; ground reference is M2GND."+ },+ {+ "number": "30",+ "name": "ADCINB0",+ "type": "input",+ "description": "ADC Group B channel 0 analog input (ADC full-scale 0 V to 3.3 V)."+ },+ {+ "number": "31",+ "name": "ADCINB7 (op-amp)",+ "type": "input",+ "description": "ADC Group B channel 7 analog input, labelled as op-amp channel B7 in the datasheet; ground reference is PFCGND."+ },+ {+ "number": "32",+ "name": "PFCGND",+ "type": "power_in",+ "description": "Ground pin for amplifier channel B7."+ },+ {+ "number": "33",+ "name": "GPIO27/SCITXDC",+ "type": "bidirectional",+ "description": "General-purpose I/O 27 (default GPIO) with alternate function SCITXDC (SCI-C transmit, output); inputs are not 5-V tolerant."+ },+ {+ "number": "34",+ "name": "GPIO31/CANTXA/SCITXDB/EPWM7B",+ "type": "bidirectional",+ "description": "General-purpose I/O 31 with internal pullup enabled by default, alternate functions CANTXA, SCITXDB and EPWM7B (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "35",+ "name": "GPIO30/CANRXA/SCIRXDB/EPWM7A",+ "type": "bidirectional",+ "description": "General-purpose I/O 30 with internal pullup enabled by default, alternate functions CANRXA (input), SCIRXDB (input) and EPWM7A (output); inputs are not 5-V tolerant."+ },+ {+ "number": "36",+ "name": "GPIO9/EPWM5B/SCITXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 9 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM5B and SCITXDB (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "37",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "38",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer and flash memory power pin; the single supply source when VREG is enabled, with a decoupling capacitor on each pin (value set by the system voltage regulation solution)."+ },+ {+ "number": "39",+ "name": "TEST2",+ "type": "bidirectional",+ "description": "Test pin reserved for TI; must be left unconnected."+ },+ {+ "number": "40",+ "name": "GPIO26/SCIRXDC",+ "type": "bidirectional",+ "description": "General-purpose I/O 26 (default GPIO) with alternate function SCIRXDC (SCI-C receive, input); inputs are not 5-V tolerant."+ },+ {+ "number": "41",+ "name": "GPIO29",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 (default GPIO) with alternate functions SCITXDA (output), SCLA (I2C clock, open-drain), TZ3 (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant."+ },+ {+ "number": "42",+ "name": "GPIO28/SCIRXDA/SDAA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 (default GPIO) with alternate functions SCIRXDA (input), SDAA (I2C data, open-drain) and TZ2 (input); inputs are not 5-V tolerant."+ },+ {+ "number": "43",+ "name": "GPIO18/SPICLKA/SCITXDB/XCLKOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 (default GPIO) with alternate functions SPICLKA (I/O), SCITXDB (output) and XCLKOUT (output, SYSCLKOUT/4 at reset, disabled when XCLKOUTDIV = 3); inputs are not 5-V tolerant."+ },+ {+ "number": "44",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 (default GPIO) with alternate functions SPISOMIA (I/O), EQEP1I (I/O), TZ3 (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant."+ },+ {+ "number": "45",+ "name": "GPIO8/EPWM5A/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 8 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM5A and ADCSOCAO (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "46",+ "name": "GPIO25",+ "type": "bidirectional",+ "description": "General-purpose I/O 25 (default GPIO) with no peripheral alternate functions listed; inputs are not 5-V tolerant."+ },+ {+ "number": "47",+ "name": "GPIO16/SPISIMOA/EQEP1S/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 (default GPIO) with alternate functions SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (input); inputs are not 5-V tolerant."+ },+ {+ "number": "48",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 (default GPIO) with alternate functions TZ1 (input), CTRIPM1OUT (output) and SCITXDA (output); inputs are not 5-V tolerant."+ },+ {+ "number": "49",+ "name": "GPIO7/EPWM4B/SCIRXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM4B (output) and SCIRXDA (input); inputs are not 5-V tolerant."+ },+ {+ "number": "50",+ "name": "GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM4A (output), EPWMSYNCI (input) and EPWMSYNCO (output); inputs are not 5-V tolerant."+ },+ {+ "number": "51",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 is left unconnected if not used."+ },+ {+ "number": "52",+ "name": "X1",+ "type": "input",+ "description": "On-chip 1.8-V crystal oscillator input; a crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used."+ },+ {+ "number": "53",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "54",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used)."+ },+ {+ "number": "55",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 (default GPIO) with alternate functions XCLKIN (external 3.3-V oscillator input, not gated by the mux), SPISTEA (I/O), SCIRXDB (input) and ECAP1 (I/O); can glitch at power-up when the internal VREG is used."+ },+ {+ "number": "56",+ "name": "GPIO39/SCIRXDC/CTRIPPFCOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 39 (default GPIO) with alternate functions SCIRXDC (input) and CTRIPPFCOUT (output); inputs are not 5-V tolerant."+ },+ {+ "number": "57",+ "name": "GPIO38",+ "type": "bidirectional",+ "description": "General-purpose I/O 38 (default XCLKIN selection) with JTAG TCK function (input, internal pullup); can glitch at power-up when the internal VREG is used, and the XCLKIN path must not be enabled while TCK is in use during debug."+ },+ {+ "number": "58",+ "name": "GPIO37/TDO",+ "type": "tri_state",+ "description": "General-purpose I/O 37 with JTAG scan data output TDO (O/Z, 8 mA drive), shifted out on the falling edge of TCK; can glitch at power-up when the internal VREG is used."+ },+ {+ "number": "59",+ "name": "GPIO35/TDI",+ "type": "bidirectional",+ "description": "General-purpose I/O 35 with JTAG test data input TDI (internal pullup), clocked into the selected register on the rising edge of TCK; does not have a glitch-free output at power-up."+ },+ {+ "number": "60",+ "name": "GPIO36/TMS",+ "type": "bidirectional",+ "description": "General-purpose I/O 36 with JTAG test-mode select TMS (internal pullup), clocked into the TAP controller on the rising edge of TCK; does not have a glitch-free output at power-up."+ },+ {+ "number": "61",+ "name": "GPIO11/EPWM6B/SCIRXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 11 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM6B (output) and SCIRXDB (input); inputs are not 5-V tolerant."+ },+ {+ "number": "62",+ "name": "GPIO5/EPWM3B/SPISIMOA/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM3B (output), SPISIMOA (I/O) and ECAP1 (I/O); inputs are not 5-V tolerant."+ },+ {+ "number": "63",+ "name": "GPIO4/EPWM3A",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM3A (output); inputs are not 5-V tolerant."+ },+ {+ "number": "64",+ "name": "GPIO40/EPWM7A",+ "type": "bidirectional",+ "description": "General-purpose I/O 40 with internal pullup enabled by default and alternate function EPWM7A (output); inputs are not 5-V tolerant."+ },+ {+ "number": "65",+ "name": "GPIO10/EPWM6A/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 10 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM6A and ADCSOCBO (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "66",+ "name": "GPIO3/EPWM2B/SPISOMIA",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM2B (output) and SPISOMIA (I/O); inputs are not 5-V tolerant."+ },+ {+ "number": "67",+ "name": "GPIO2/EPWM2A",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM2A (output); inputs are not 5-V tolerant."+ },+ {+ "number": "68",+ "name": "GPIO1/EPWM1B/CTRIPM1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 (PWM-capable pin, pullup not enabled at reset) with alternate functions EPWM1B and CTRIPM1OUT (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "69",+ "name": "GPIO0/EPWM1A",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 (PWM-capable pin, pullup not enabled at reset) with alternate function EPWM1A (output); inputs are not 5-V tolerant."+ },+ {+ "number": "70",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer and flash memory power pin; the single supply source when VREG is enabled, with a decoupling capacitor on each pin (value set by the system voltage regulation solution)."+ },+ {+ "number": "71",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator enable with internal pulldown; tie directly to VSS to enable the internal 1.8-V VREG, or tie directly to VDDIO to disable it and use an external 1.8-V supply."+ },+ {+ "number": "72",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "73",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values may be used)."+ },+ {+ "number": "74",+ "name": "GPIO34/CTRIPPFCOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 with alternate function CTRIPPFCOUT (output); this pin is not glitch-free at power-up (GPIO34 to GPIO38 and GPIO19 do not have glitch-free I/Os)."+ },+ {+ "number": "75",+ "name": "GPIO15/TZ1/CTRIPM1OUT/SCIRXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 15 (default GPIO) with alternate functions TZ1 (input), CTRIPM1OUT (output) and SCIRXDB (input); inputs are not 5-V tolerant."+ },+ {+ "number": "76",+ "name": "GPIO13/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 13 (default GPIO) with alternate function TZ2 (trip zone input 2); inputs are not 5-V tolerant."+ },+ {+ "number": "77",+ "name": "GPIO14/TZ3/CTRIPPFCOUT/SCITXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 14 (default GPIO) with alternate functions TZ3 (input), CTRIPPFCOUT (output) and SCITXDB (output); inputs are not 5-V tolerant."+ },+ {+ "number": "78",+ "name": "GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 20 with internal pullup enabled by default, alternate functions EQEP1A (input), EPWM7A and CTRIPM1OUT (outputs); inputs are not 5-V tolerant."+ },+ {+ "number": "79",+ "name": "GPIO21/EQEP1B/EPWM7B",+ "type": "bidirectional",+ "description": "General-purpose I/O 21 with internal pullup enabled by default, alternate functions EQEP1B (input) and EPWM7B (output); inputs are not 5-V tolerant."+ },+ {+ "number": "80",+ "name": "GPIO23/EQEP1I/SCIRXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 23 (default GPIO) with alternate functions EQEP1I (I/O) and SCIRXDB (input); inputs are not 5-V tolerant."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Datasheet lists VREFLO as type I and says it is always tied to ground; kept as input per the datashe; ADCINA0 and VREFOUT share pin 18 (VREFOUT is the buffered DAC reference output); typed as input, whi; Open-drain pins (XRS I/OD, SDAA/SCLA I/OD) are mapped to bidirectional because KiCad open-collector "+ ],+ "pages_sent": 30,+ "cost_usd": 0.2307,+ "at": "2026-10-07T21:48:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28054f",+ "pages": 159,+ "sha256": "aaaaedb6c548633c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320f28055pnt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f782bdbc6327d920be33e2b9906695d7c3690117933775c3f145eac71f2013ac",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320f28055pnt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ba4fa530c3df243fff077c71e6d78cd41623ff38958504bf0d0c05e069b53cd8",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}